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| ethercat slave controller for i ntegrated c i rcu i ts tmc8462 datasheet document revision v1.4 ? 2018-may -09 the tmc8462 is a complete ethercat ? slave controller optimized for real time. i t comprises all blocks required for an ethercat slave including two 100-mbit phys, a dual switch regulator power supply and 24v capable high voltage i /os for industrial environments. timer, watchdog, pwm and sp i / ii c master units allow for enhanced capabilities either in device emulation mode or in combination with an external cpu. features ? standard compliant ethercat ? slave ? dual i ntegrated 100-mbit ethernet phy ? sp i process data i nterface (pd i ) ? i o block with 24 multi-function i /os ? i nternal 3.3v plus free 5v-24v switch regulator ? 8 high voltage i /os (up to 35v, 100ma) ? multifunction block comprises watch- dog, 4 pwm outputs and step/dir generator ? direct ethercat access to external adcs, stepper motor controllers, etc. ? ethercat-p compatible voltage range applications ? factory automation ? process automation ? communication modules ? i ndustrial i ot ? i ndustry 4.0 ? sensors & encoders ? robotics ? i ndustrial motion control ? building automation simpli 1 ed block diagram ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at: www.trinamic.com read entire documentation.
tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 2 / 204 contents 1 product features 5 2 order codes 6 3 principles of operation / key concepts 7 3.1 general device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 ethercat slave controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 multi-function and control i o block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 analog and high voltage block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 i nterfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6 software- and tool-support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device pin de 1 nitions 15 4.1 pinout and pin coordinates of tmc8462-ba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 device usage and handling 23 5.1 process data i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 sp i protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.2 timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 mfc i o control i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.1 sp i protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.2 timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.3 sharing bus lines with the pd i sp i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 ethernet physical layer connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 external circuitry and applications examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.1 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.2 supply filtering for pll supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.3 phy power regulator filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.4 external circuit for fixed switching regulator 0 . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.5 external circuit for adjustable switching regulator 1 . . . . . . . . . . . . . . . . . . . . 34 5.4.6 minimum external supply circuit for single 3.3v supply . . . . . . . . . . . . . . . . . . 35 5.4.7 minimum external supply circuit for single 5v supply . . . . . . . . . . . . . . . . . . . 36 5.4.8 minimum external supply circuit for single supply >5v . . . . . . . . . . . . . . . . . . 37 5.4.9 typical power supply chain using both buck converters . . . . . . . . . . . . . . . . . 38 5.4.10 status led circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.11 s ii eeprom circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.12 considerations on phy to phy connection . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 ethercat slave controller description 40 6.1 general ethercat i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 overview of available chip features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3 ethercat register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4 ethercat register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4.1 esc i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4.2 station address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.3 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.4 data link layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.5 application layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.4.6 pd i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4.7 i nterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4.8 error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.9 watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 3 / 204 6.4.10 s ii eeprom i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.11 esc parameter ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4.12 m ii management i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.13 fmmus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4.14 syncmanagers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.4.15 distributed clocks receive times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.4.16 distributed clocks time loop control unit . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4.17 distributed clocks cyclic unit control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.4.18 distributed clocks sync out unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.4.19 distributed clocks latch i n unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.4.20 distributed clocks syncmanager event times . . . . . . . . . . . . . . . . . . . . . . . . 107 6.4.21 esc speci 1 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.4.22 process data ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7 mfc i o block description 110 7.1 general i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.2 mfc i o register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.3 mfc i o register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.3.1 i ncremental encoder i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.3.2 sp i master i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.3.3 i 2c master i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.3.4 step and direction signal generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.3.5 pwm unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.3.6 general purpose i /os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.3.7 dac unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.3.8 i rq control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.3.9 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.3.10 high voltage status and general control . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.3.11 application layer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.4 s ii eeprom mfc i o block parameter map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.5 s ii eeprom mfc i o crossbar mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.6 s ii eeprom mfc i o high voltage i o (hv i o) con 1 guration . . . . . . . . . . . . . . . . . . . . . 152 7.7 s ii eeprom mfc i o switching regulator con 1 guration . . . . . . . . . . . . . . . . . . . . . . . 153 7.8 s ii eeprom mfc i o memory block mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.9 s ii eeprom mfc i o register con 1 guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.10 mfc i o es i /xml con 1 guration block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.11 mfc i o i ncremental encoder block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.12 mfc i o sp i master block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.12.1 sp i examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7.13 mfc i o i 2c master block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.13.1 i 2c example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.14 mfc i o step and direction block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.15 mfc i o pwm block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.16 mfc i o dac block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.17 mfc i o general purpose i o block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.18 mfc i o i rq block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.19 mfc i o watchdog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.20 mfc i o emergency switch i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.21 mfc i o analog and high voltage block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 7.21.1 multi voltage high current i /o lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 7.21.2 switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.21.3 analog block status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 4 / 204 8 electrical ratings 190 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 8.2 operational ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.3 dc characteristics and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.3.1 high voltage i /o block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.3.2 switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 8.3.3 digital i os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 9 manufacturing data 194 9.1 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 9.2 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 9.3 board and layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10 abbreviations 197 11 tmc8462-ba errata 199 11.1 case 1 C lost link counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12 figures i ndex 200 13 tables i ndex 201 14 revision history 204 14.1 i c revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.2 document revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 5 / 204 1 product features tmc8462 is an advanced ethercat slave controller device used for ethercat communication. i t provides the interface for data exchange between ethercat master and the slave s local application controller. i n addition, tmc8462 provides complex i o functions paired with high voltage features and integrated 100bit ethernet phys. advantages: ? fully standard compliant and proven ethercat engine ? highly integrated with highest feature count vs. package size ? license-free & royalty-free ? high voltage & robust ? saves board space & reduces bom ? long-term availability major features: ? ethercat slave controller with 2 ports for bus interfacing, 8 fmmu & 8 sync managers, distributed clocks with 64 bit, 16kbyte of process data memory, external i 2c eeprom, sp i process data i nterface (pd i ), optional device emulation ? tr i nam i c multi-function control and i o block with 24 con 1 gurable i o ports for complex real-time i o functions (gp i os, pwm, step/direction, i 2c, sp i , dac, incremental encoder) including 8 high voltage i os ? tr i nam i c high voltage block with 8 short circuit protected push-/pull or open drain high voltage i os for up to 24v and 100ma drive current ? two integrated 500ma step down switching voltage regulators with one being 1 xed at 3.3v and one being programmable between 5v and 24v ? i nternal 1.8v linear regulator for core voltage generation ? two integrated 100-mbit ethernet phys to directly connect to twisted pair copper or back-to-back directly to another phy ? simple con 1 guration of ethercat slave controller and multi-function control and i o block via eeprom ? 3.3v digital i o voltage ? working with a single supply voltage depending on application: 3.3v only or 5v to 35v (5v, 12v, or 24v typical) ? i ndustrial temperature range -40c to +85c ? i ntegrated temperature measurement and over-temperature shutdown ? package: 9mm x 9mm bga packge with 121 pins and 0.75mm pitch ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 6 / 204 2 order codes order code description size tmc8462-ba tmc8462 advanced ethercat ? slave controller in 121 pin bga package with 0.75mm pitch 9mm x 9mm tmc8462-eval evaluation board for tmc8462-ba, compatible with the modu- lar LANDUNGSBRUECKE system, rj45 twisted pair copper interface 79mm x 85mm LANDUNGSBRUECKE mcu board 85mm x 55mm tmc8462-bob-eth breakout board (bob) for tmc8462-ba, with 0.1" header rows, reference clock source, s ii -eeprom, and rj45 twisted pair cop- per transceiver interface 2.0" x 1.5" table 1: tmc8462 order codes trademark and patents ethercat ? is a registered trademark and patented technology, licensed by beckho ? automation gmbh, germany. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 7 / 204 3 principles of operation / key concepts tmc8462 is a highly integrated as i c providing the interface between the ethernet-based ethercat real-time 1 eld bus and the local application. i ts extended digital and high voltage feature set provides additional functions to the ethercat slave. 3.1 general device architecture figure 1 shows the general device architecture and major connections of tmc8462. the four function blocks ethercat slave controller, multi-function control and i o, analog and high voltage, and ethernet phys are introduced in the following sub-sections. for operation, a stable 100mhz clock source, an ii c eeprom, and power supply for i o and high voltage operation are required (if the high voltage features are used). an application controller, which also runs the ethercat slave stack, connects to the sp i interfaces. the application and onboard peripherals can be controlled by the application controller or the multi-function control and i o block. figure 1: general device architecture ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 8 / 204 3.2 ethercat slave controller tmc8462 contains a standard-conform ethercat slave controller (esc) providing real-time ethercat mac layer functionality to ethercat slaves. i t connects via m ii interface to standard ethernet phys and provides a digital control interface to a local application controller while also providing the option for standalone operation. the esc part of tmc8462 provides the following ethercat-related features. more information is available in section 6 . ? two internal 100mbit ethernet phys ? eight fieldbus memory management units (fmmu) ? eight sync managers (sm) ? 16 kbyte of process data ram (pdram) ? 64b bit distributed clocks support ? i 2c interface for external eeprom for esc con 1 guration ? sp i process data i nterface (pd i ) with 30mbit/s ? proven ethercat state machine (esm) ? device emulation mode 3.3 multi-function and control i o block i n addition to the ethercat functionality, the tmc8462 comes with a dedicated function block providing a con 1 gurable set of complex real-time i o functionality for smart (embedded) ethercat slave systems. this i o functionality is called multi-function control and i o block (mfc i o). i ts special focus is on motor and motion control while it is not limited to this application area. the mfc i o block combines various functional sub blocks that are helpful in an embedded design to reduce complexity, to simplify bill of materials (bom), and to provide hardware acceleration to compute intensive or time critical tasks. more information is available in section 7 . con 1 gurable i o ports the whole mfc i o block provides in total 24 i o ports that can be con 1 gured and assigned to any of the available functional units inside the mfc i o block. i f not used, each i o port can be tristated. general purpose i os up to sixteen (16) general purpose i os are available. each i o can be con 1 gured either as input or as output. for the outputs, a safe state can be con 1 gured which is used in case of emergency event. i ncremental encoder i nterface con 1 gurable incremental encoder interface with 32 bit position regis- ters, single-ended or di ? erential inputs, con 1 gurable counting constant for di ? erent resolutions, con 1 g- urable polarity and n-signal behavior. step/direction generator block the step and direction unit provides upt to 3 independent channels. various con 1 guration options and modes allow for example for continuous or one-shot mode, reading of the internal total step counters, pre-loading the next step frequency to be used at a certain counter value. the step and direction outputs signals can be single-ended or di ? erential. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 9 / 204 pwm block the integrated pwm block provides up to 4 pwm channels. pwm frequency and duty cycle as well as polarities and dead times are con 1 gurable. the outputs can be con 1 gured for a safe state in case of emergency. generic sp i master i nterface the tmc8462 provides a generic sp i master interface to connect to on- or o ? -board sp i slave peripherals like adcs, sensors, or motor drivers. the sp i master interface is fully con 1 gurable and o ? ers 4 slave select lines. generic i 2c master i nterface a generic i 2c master interface is also available in tmc8462 to connect to i 2c slaves. the i 2c bus speed is con 1 gurable. digital dac a simple digital 16 bit dac channel is available which requires an external rc circuit for operation. safety functions the following safety functions are available with the tmc8462 ? con 1 gurable watchdog functionality for the mfc i o block to monitor internal and external signals as well as ethercat activity. this block is fully con 1 gurable. ? a general emergency switch input can be activated. for critical outputs, a safe state can be con 1 gured which is used when the emergency switch triggers. ? a common i rq signal is available at the mfc i o block which can be mapped to various events of the mfc i o block. the i rq events can be processed by a local application controller. 3.4 analog and high voltage block tmc8462 has an integrated powerful high voltage sub block that provides analog functions and high voltage support to your ethercat slave. the integrated high voltage capabilities allow for bom reduction and save board space. more information is available in section 7.21 . high voltage ports 8 of the 24 con 1 gurable i o ports of the mfc i o block are high voltage i o ports. for pure digital systems operating at 3.3v or 5v these ports can simply be used as standard i o ports. when using a higher supply voltage at the v i ox inputs the high voltage ports can be used at up to 35v (5v, 12v, 24v typical). the 8 high voltage ports are grouped into 3 groups with 2, 3, and 3 ports. each group can be used a di ? erent supply voltage level using v i o1, v i o2, and v i o3 inputs. each high voltage port has a short circuit protected push-/pull or open drain output stage with 100ma drive current (ca. 200 ma short time) and can be combined with any signal of the mfc i o block functions. the outputs slope can be controlled. an optional input 1 lter is selectable as well as pull downs or pull ups with 100 a . the high voltage ports have an over-temperature shutdown. warn i ng when driving inductive loads a freewheeling diode must be provided to the high voltage i /o pins to prevent from latch-up. switching regulators two switching regulators (buck regulators) are integrated into tmc8462 C sw0 and sw1. both are capable of driving up to 500ma. sw0 generates a 1 xed 3.3v rail for internal and external logic supply. sw1 is programmable between 3.3v and vs (up to 24v) and can be used for peripheral supply, e.g, to generate a 5v encoder supply. each switching regulator comes with a separate over-temperature shutdown. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 10 / 204 single supply operation tmc8462 is designed to work with a single external power supply rail. all required supply voltages are generated internally. the required external supply rail depends on the application scenario (between 3.3v and 24v). 3.5 i nterfaces field bus i nterface tmc8462 contains 2 integrated 100-mbit ethernet phys and directly connects to the 1 eld bus using an external transformer circuit. i n addition, the phy interfaces of two tmc8462 devices can also be connected directly to allow back-to-back connection with only low part count and a small circuit. this is useful when extending the ethercat bus on the board or to a another slave close by. esc process data i nterface the esc part can be accessed via the so-called process data i nterface (pd i ). tmc8462 comes with an sp i pd i . besides the standard sp i bus lines additional control signals belong to the sp i pd i , which are further described in section 5.1 .. mfc i o control i nterface the mfc i o block of tmc8462 can be accessed from ethercat master side or from the local application controller. for connection to the local application controller, a second sp i interface C the mfc i o sp i C is provided. the protocol used nearly identical to the sp i pd i interface. additional information on the mfc i o sp i is given in section 5.2 . eeprom i nterface the eeprom interface is intended to be a point-to-point interface between tmc8462 and eeprom with tmc8462 being the master. i f other i 2c masters are required to access the i 2c bus, tmc8462 must be held in reset state, for example for in-circuit-programming of the eeprom. during operation, the application controller must tristate its i 2c interface. depending on the eeprom size the addressing mode must be properly set using the prom_s i ze con 1 guration pin. con 1 guration i nputs hard-wired con 1 guration pins are available at the tmc8462, which are used to con 1 gure various options related to the hardware con 1 guration and application scenario and which will not change. these pins are prom_s i ze, pd i _shared_sp i _bus, and dev i ce_emulat i on. more information on these con 1 guration pins and signals is given in section 4.2 and section 5 . 3.6 software- and tool-support tr i nam i c s ethercat slave controller family comes with extensive hardware and software tool support to get started quickly. evaluation board an evaluation board is available for the tmc8462 with standard rj45 connectors and transformers for interfacing twisted pair copper (tpc) media. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 11 / 204 figure 2: tmc8462 evaluation board the complete board design 1 les are available for download and can be used as reference. all information is available for download on the speci 1 c product page on tr i nam i c s website at http://www.trinamic.com/products/integrated-circuits/evalboards . breakout board (bob) besides the evaluation board another smaller breakout board is available. i t allows for easy integration into own systems or connection to a prototyping platform. the breakout board provides the bus interface along with the esc and requires an appropriate supply and controller connection. the bob comes with standard rj45 connectors to connect to tpc using the tmc8462 esc with integrated ethernet phys. tmc8462 is functionally equal to the tmc8461. the di ? erence is in using external phys vs. integrated phys. the complete board design 1 les are available for download and can be used as reference. all information is available for download from the evaluation board section on tr i nam i c s website at https://www.trinamic.com/support/eval-kits/ . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 12 / 204 figure 3: tmc8462 breakout board for rj45 and tpc tr i nam i c technology access package i n addition, a comprehensive source code and software package C tr i nam i c technology access package (ttap) C is available for download to get started quickly with own code. the ttap is available at https://www.trinamic.com/support/software/access-package/ . tmcl- i de the tmcl- i de is tr i nam i c s primary tool (for windows pcs) to control tr i nam i c modules and evaluation boards. besides, it provides feature like remote 1 rmware updates, module monitoring options, and speci 1 c wizard support. the tmcl- i de can be used along with tr i nam i cs modular evaluation board system. figure 4: tmcl- i de ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 13 / 204 the latest version and additional information is available for download from tr i nam i c s website at http://www.trinamic.com/software-tools/tmcl-ide . ethercat slave con 1 guration con 1 guration of the ethercat slave controller is done during boot time with con 1 guration information read from the s ii eeprom after reset or power cycling. this information must be (pre)programmed into the s ii eeprom. this can be done via the ethercat master using a so-called ethercat slave i nformation (es i ) 1 le in standardized xml format. the s ii eeprom can also be (re)written using the local application controller. es i con 1 guration wizard the tmcl- i de contains a wizard to assist users with the con 1 guration of the tmc8462 various mfc i o functions. the wizard shows available and allowed options and provides xml code snippets for the es i 1 le for the s ii eeprom as well as generic c-code blocks. these can be used as starting point for own 1 rmware development for the application controller. figure 5: con 1 guration wizard example C mfc i o block con 1 guration ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 14 / 204 figure 6: con 1 guration wizard example C s ii eeprom content and c-code output ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 15 / 204 4 device pin de 1 nitions 4.1 pinout and pin coordinates of tmc8462-ba 1 2 3 4 5 6 7 8 9 10 11 a b c d e f g h j k l figure 7: tmc8462-ba pinout top view 4.2 signal descriptions name pin type ( i ,o,pu,pd) function general signals nreset k4 i /o low active system reset. nreset is an i /o pin. connected to vcc i o via a 10k resistor and to gnd via a 10nf capacitor if no other reset source for proper power-on reset is used. for more information see section 5.4.1 . ref_clk100_ i n l3 i 100mhz reference clock input, connect to a clock source <25ppm. clk16_out h7 o 16.6mhz auxiliary clock output. not available during reset. en_clk16_out e9 i enable signal for clk16_out: 0 = o ? , 1 = on ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 16 / 204 name pin type ( i ,o,pu,pd) function reset_out j4 o this high-active reset output is activated via ethercat register 0x0040 ), therefore reset_out has to trigger the nreset input, which clears reset_out. this connection incl. changing the polarity has to be made externally . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 17 / 204 name pin type ( i ,o,pu,pd) function eeprom i os prom_ i n i t j5 o signal indicating that eeprom has been loaded, 0 = not ready, 1 = eeprom loaded prom_clk h4 o external i 2c eeprom clock signal, use 1k pull up resistor to 3.3v prom_data h5 i /o external i 2c eeprom data signal, use 1k pull up resistor to 3v3 prom_s i ze g9 i selects between two di ? erent eeprom sizes since the communication protocol for eeprom access changes if a size > 16kbit is used (an ad- ditional address byte is required then). 0 = up to 16kbit eeprom, 1 = 32 kbit-4mbit eeprom dc synchronization i os sync_out0 d7 o distributed clocks synchronization output 0, typ- ically connect to mcu sync_out1 d6 o distributed clocks synchronization output 1, typ- ically connect to mcu latch_ i n0 c7 i latch input 0 for distributed clocks, connect to gnd if not used. latch_ i n1 c6 i latch input 1 for distributed clocks, connect to gnd if not used. leds led_run b3 o run status led, connect to green led (anode) 0 = led o ? , 1 = led on led_err c3 o error status led, connect to red led (anode) 0 = led o ? , 1 = led on l i nk_act0 d3 o link i n port status and activity, connect to green led (anode) 0 = led o ? , 1 = led on l i nk_act1 e3 o link out port status and activity, connect to green led (anode) 0 = led o ? , 1 = led on ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 18 / 204 name pin type ( i ,o,pu,pd) function process data i nterface i os to/from mcu pd i _sof h3 o ethernet start-of-frame if 1 pd i _eof g3 o ethernet end-of-frame if 1 pd i _sp i _csn l4 i chip select signal of the process data interface pd i _sp i _sck k3 i serial clock signal of the process data interface pd i _sp i _mos i l5 i serial data out signal of the process data inter- face pd i _sp i _m i so k5 o serial data in signal of the process data interface pd i _sp i _ i rq j3 o i nterrupt signal for primary process data inter- face, connect to mcu pd i _wdstate g4 o ethercat watchdog state, 0: expired, 1: not ex- pired pd i _wdtr i gger f4 o ethercat watchdog trigger if 1 pd i _emulat i on j7 i selects between pd i interface (sp i ) or standalone operation with state machine emulation inside esc. has weak internal pull down. 0 = default, pd i interface active, 1 = standalone operation, state machine emulation in slave controller mfc i o control i nterface i os mfc_ctrl_sp i _csn d4 i chip select signal of the mfc i o control interface mfc_ctrl_sp i _sck e4 i serial clock signal of the mfc i o control interface mfc_ctrl_sp i _mos i c4 i serial data out signal of the mfc i o control inter- face mfc_ctrl_sp i _m i so e7 o serial data in signal of the mfc i o control inter- face mfc_ i rq e6 o mfc i o block i rq for con 1 gurable events, connect to mcu, high active mfc_nes c5 i low active (not) emergency stop/switch/halt (to bring pwm or other outputs into a safe state), the event must be cleared actively, has weak in- ternal pull down, must be driven high for normal operation pd i _shared_bus f9 i selects between separate sp i buses (m i so, mos i , sck) or one sp i bus with two cs lines for the pd i and mfc ctrl sp i interface: 0 = two separate sp i buses, 1 = one shared sp i bus using the pd i _sp i _x bus lines ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 19 / 204 name pin type ( i ,o,pu,pd) function mfc i os mfc i o00 j8 i /o mfc i o block low voltage i /o mfc i o01 j9 i /o mfc i o block low voltage i /o mfc i o02 j10 i /o mfc i o block low voltage i /o mfc i o03 j11 i /o mfc i o block low voltage i /o mfc i o04 h8 i /o mfc i o block low voltage i /o mfc i o05 h9 i /o mfc i o block low voltage i /o mfc i o06 h10 i /o mfc i o block low voltage i /o mfc i o07 h11 i /o mfc i o block low voltage i /o mfc i o08 d8 i /o mfc i o block low voltage i /o mfc i o09 d9 i /o mfc i o block low voltage i /o mfc i o10 d10 i /o mfc i o block low voltage i /o mfc i o11 d11 i /o mfc i o block low voltage i /o mfc i o12 c8 i /o mfc i o block low voltage i /o mfc i o13 c9 i /o mfc i o block low voltage i /o mfc i o14 c10 i /o mfc i o block low voltage i /o mfc i o15 c11 i /o mfc i o block low voltage i /o mfc high voltage i os mfc_hv0 (mfc i o16) a4 i /o mfc i o block high voltage i /o mfc_hv1 (mfc i o17) a5 i /o mfc i o block high voltage i /o mfc_hv2 (mfc i o18) a6 i /o mfc i o block high voltage i /o mfc_hv3 (mfc i o19) a7 i /o mfc i o block high voltage i /o mfc_hv4 (mfc i o20) a8 i /o mfc i o block high voltage i /o mfc_hv5 (mfc i o21) a9 i /o mfc i o block high voltage i /o mfc_hv6 (mfc i o22) a10 i /o mfc i o block high voltage i /o mfc_hv7 (mfc i o23) a11 i /o mfc i o block high voltage i /o ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 20 / 204 name pin type ( i ,o,pu,pd) function mfc high voltage i o supplies v i o1 b5 i mfchv i o block 1 supply voltage v i o2 b7 i mfchv i o block 2 supply voltage v i o3 b9 i mfchv i o block 3 supply voltage gnd i o1 b6 i mfchv i o block 1 ground, connect to gnd gnd i o2 b8 i mfchv i o block 2 ground, connect to gnd gnd i o3 b10 i mfchv i o block 3 ground, connect to gnd device supply and ground vs b11 i supply voltage, use a 100nf 1 lter capacitor vcc i o e10, f10, i i /o supply voltage, use a 100nf 1 lter capacitor per pin g10, f11 vcc_core f6, g6, i core supply voltage, connect to vdd1v8_out, use a 100nf 1 lter capacitor per pin f7, g7 pllclk_vcc i o k6 i pll supply voltage, connect to vcc i o through a 1 lter (r/l/c) tstclk_select h6 i test input, always connect to vcc i o for nor- mal operation gnd c1, f1, i supply ground j1, a3, b4, f5, g5, e8, f8, g8 pllclk_gnd j6 i pll supply ground, connect to gnd voltage regulator i os vdd1v8_out g11 o output of internal 1.8v regulator, use a 100nf 1 lter capacitor vdd5_out e11 o output of internal 5v regulator, use a 100nf 1 l- ter capacitor if vs 5v ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 21 / 204 name pin type ( i ,o,pu,pd) function switching regulator 0 i os vs0 l7 i switching regulator 0 supply voltage, switching regulator 0 provides a 1 xed 3.3v output. gnd0 l9 i switching regulator 0 ground, connect to gnd sw0 l8 o switching regulator 0 output, 1 xed 3.3v sw_d i ode k7 i switching regulator 0 internal diode, connect to sw0 only if vs0 is at or below 5v gnd_d i ode k8 i switching regulator 0 internal diode ground, con- nect to gnd switching regulator 1 i os vs1 l11 i switching regulator 1 supply voltage, switching regulator 1 provides an adjustable output volt- age. gnd1 k9 i switching regulator 1 ground, connect to gnd sw1 l10 o switching regulator 1 output, adjustable vout k10 i switching regulator 1 inductor ringing suppres- sion feedback vout_fb k11 i switching regulator 1 feedback voltage, 1.2v typi- cally bus i nterface 0 i os ( ethercat i n port ) tn0 d1 o negative pin of di ? erential transmit output pair tp0 e1 o positive pin of di ? erential transmit output pair rn0 a1 i negative pin of di ? erential receive output pair rp0 b1 i positive pin of di ? erential receive output pair regout0 a2 o regulator power output, use a 10uf and 0.1uf for 1 ltering power noise mclk f2 o phy management clock, leave open if not needed md i o f3 i /o, pu phy management data, use 4k7 pull up resistor to vcc i o (3.3v) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 22 / 204 name pin type ( i ,o,pu,pd) function bus i nterface 1 i os ( ethercat out port ) tn1 k1 i o negative pin of di ? erential transmit output pair tp1 l1 i o positive pin of di ? erential transmit output pair rn1 g1 i o negative pin of di ? erential receive output pair rp1 h1 i o positive pin of di ? erential receive output pair regout1 l2 o regulator power output, use a 10uf and 0.1uf for 1 ltering power noise test pins only tst_mode e5 i test mode enable, connect to gnd tst_ana d5 o analog test output, leave open rxclk0 d2 i o clock test pin, leave open rxclk1 g2 i o clock test pin, leave open txclk0 e2 i o clock test pin, leave open txclk1 h2 i o clock test pin, leave open rxdv0 b2 i , pd test pin, leave open for normal operation rxdv1 k2 i , pd test pin, leave open for normal operation txer0 c2 i , pd test pin, leave open for normal operation txer1 j2 i , pd test pin, leave open for normal operation clko_100 l6 o 100mhz clock output table 2: pin and signal description for tmc8462-ba ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 23 / 204 5 device usage and handling 5.1 process data i nterface the process data i nterface (pd i ) is an sp i interface with a clock frequency of up to 30 mhz. the esc registers and the process data ram can be accessed from an external microcontroller using this interface. the interface can be con 1 gured via the eeprom, however it is recommended to use the default con 1 g- uration (sp i mode 3 with low active chip select). for further details, see the esc sp i slave con 1 guration registers in section 6 . additionally, some signals are available that can be evaluated by the application controller. figure 8: pd i control signals tmc8462 pin description typical pin on a mcu pd i _sp i _csn sp i chip select for the tmc8462 pd i ssx pd i _sp i _sck sp i master clock sck pd i _sp i _mos i master out slave in data mos i pd i _sp i _m i so master in slave out data m i so pd i _sp i _ i rq con 1 gurable i rq from pd i general purpose i nput pd i _emulat i on 0: default mode for complex slaves, state machine changes processed in microcontroller 1 rmware (ssc); 1: device emulation mode for, e.g., simple slaves, state machine changes directly handled in the esc general purpose output or connected to either ground or 3.3v. pd i _sof i ndicates start of an ethernet/ethercat frame (m ii _rxdv = 1 ) general purpose i nput ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 24 / 204 tmc8462 pin description typical pin on a mcu pd i _eof i ndicates end of an ethernet/ethercat frame general purpose i nput pd i _wdstate 0: watchdog expired; 1: watchdog not expired general purpose i nput pd i _wdtr i gger watchdog triggered if 1 general purpose i nput table 3: pd i signal description 5.1.1 sp i protocol description each sp i datagram contains a 2- or 3-byte address/command part and a data part. for addresses below 0x2000 , the 2-byte addressing mode can be used, the 3 byte addressing mode can be used for all addresses. c2 c1 c0 command 0 0 0 nop (no operation, no following data bytes) 0 0 1 reserved 0 1 0 read 0 1 1 read with wait state byte 1 0 0 write 1 0 1 reserved 1 1 0 address extension, signaling 3 byte mode 1 1 1 reserved table 4: pd i sp i commands figure 9: pd i sp i 2 byte addressing ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com a12 a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 c2 c1 c0 address command a12 a11 a9 a8 a7 a6 a5 a10 a4 a3 a2 a1 a0 c2 c1 c0 byte 0 byte 1 tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 25 / 204 figure 10: pd i sp i 3 byte addressing unless highest performance is required, using only the 3-byte addressing mode and the read with wait state command is recommended since it reduces the need for special cases in the software. during the address/command bytes, the esc replies with the contents of the event request registers ( 0x0220 , 0x0221 and in 3 byte addressing mode 0x0222 ). command 0 - nop this command can be used for checking the event request registers and resetting the pd i watchdog without a read or write access. example datagram: 0x00 0x00 example reply (al control event bit is set): 0x01 0x00 command 2 - read with the read command, an arbitrary amount of data can be read from the device. the 1 rst byte read is the data from the address given by the address/command bytes. with every read byte, the address is incremented. during the data transfer, the sp i master sends 0x00 except for the last byte where a 0xff is sent. when using this command, a pause of 240ns or more must be included between the address/command bytes and the data bytes for the esc to fetch the requested data. example datagram (read from address 0x0120 and 0x0121 ): 0x09 0x02 0x00 0xff example reply (operational state requested): 0x01 0x00 0x08 0x00 command 3 - read w i th wa i t state byte this command is similar to the read command with an added dummy byte between the address/command part and the data part of the datagram. this allows enough time to fetch the data in any case. example datagram (read starting at address 0x3400 ): 0xa0 0x06 0x2c 0xff 0x00 0x00 0x00 0xff example reply ( 0xxx is unde 1 ned data): 0x00 0x00 0x00 0xxx 0x44 0x41 0x54 0x41 command 4 - wr i te the write command allows writing of an arbitrary number of bytes to writable esc registers or the process data ram. i t requires no wait state byte or delay after the address/command bytes. after every transmitted byte, the address is incremented. example datagram (write starting at address 0x4200 ): 0x10 0x06 0x50 0x4c 0x48 example reply ( 0xxx is unde 1 ned data): 0x00 0x00 0x00 0xxx 0xxx address 0x4200 now contains 0x4c , address 0x4201 contains 0x48 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com a15 a14 a13 a12 a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 c2 c1 c0 address command a12 a11 a9 a8 a7 a6 a5 a10 a4 a3 a2 a1 a0 1 1 0 a15 a14 a13 c2 c1 c0 0 0 byte 0 byte 1 byte 2 address extension command reserved tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 26 / 204 command 6 - address extens i on the address extension command is mainly used for the 3-byte addressing mode as shown in figure 10 . for sp i masters that can only process datagrams with an even number of bytes, it might be necessary to pad the datagram to an even number of bytes. this can be achieved by duplicating the third byte of the 3-byte address/command part and using the address extension command in all but the last duplicate. for example, a sp i master that is only capable of transmitting a multiple of 4 bytes cannot use the example datagram for a write access above since it contains 5 bytes. with three added padding bytes, the master has to transmit two 4-byte groups. example datagram (write starting at address 0x4200 ): 0x10 0x06 0x58 0x58 0x58 0x50 0x4c 0x48 example reply ( 0xxx is unde 1 ned data): 0x00 0x00 0x00 0xxx 0xxx 0xxx 0xxx 0xxx 5.1.2 timing example this example shows a generic read access with wait state and 2 byte addressing. all con 1 gurable options are shown. the delays between the transferred bytes are just to show the byte boundaries and are not required. figure 11: sp i timing example ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com csn active low csn acti ve high sck mode 0 sck mode 1 sck mode 2 sck mode 3 miso mode 1/3 late sample s i7 i6 i 5 i 4 i 3 i 2 i 1 i0 i 15 i 14 i 13 i 12 i 11 i 10 i9 i 8 d7 d6 d5 d4 d 3 d 2 d 1 d0 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 miso mode 1/3 normal sample s i 7 i 6 i 5 i4 i3 i2 i1 i 0 i 15 i 14 i 13 i 12 i 11 i 10 i 9 i8 d 7 d 6 d 5 d 4 d 3 d2 d1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 miso mode 0/2 late sample s i7 i6 i 5 i 4 i 3 i 2 i 1 i0 i 15 i 14 i 13 i 12 i 11 i 10 i9 i 8 d7 d6 d5 d4 d 3 d 2 d 1 d0 d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 mosi a 12 a 11 a 10 a 9 a 8 a 7 a6 a5 a 4 a 3 a2 a1 a0 c2 c1 c0 miso mode 0/2 normal sample i 7 i6 i5 i4 i3 i2 i 1 i 0 i 15 i 14 i 13 i 12 i 11 i 10 i 9 i8 d 7 d 6 d 5 d 4 d 3 d2 d1 d0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 27 / 204 5.2 mfc i o control i nterface the mfc i o block of the tmc8462 comes with a dedicated sp i slave interface to allow direct access from a local application controller. i t is called mfc ctrl sp i interface. this interface to the mfc i o block s functions is always available, even if the ethercat state machine is currently not in operational state (op). protocol structure and timing are identical to the pd i sp i . the mfc control sp i is a sp i mode 3 slave with low active chip select. the sp i clock frequency can be up to 30mhz. the following diagram shows all signals related to the mfc ctrl sp i interface. figure 12: mfc control signals tmc8462 pin description typical pin on a mcu mfc_ctrl_sp i _csn sp i chip select for the tmc8462 pd i ssx mfc_ctrl_sp i _sck sp i master clock sck mfc_ctrl_sp i _mos i master out slave in data mos i mfc_ctrl_sp i _m i so master in slave out data m i so mfc_ i rq con 1 gurable i rq from mfc i o block general purpose i nput pd i _shared_bus 0: separate sp i buses for pd i and mfc ctrl; 1: shared/common sp i bus for pd i and mfc ctrl with 2 csn signals using the pd i sp i bus. the sp i bus signals mfc_ctrl_sp i _sck, mfc_ctrl_sp i _m i so, mfc_ctrl_sp i _mos i can be left open in this case general purpose output or connected to either ground or 3.3v. table 5: mfc ctrl sp i signal description 5.2.1 sp i protocol description the protocol of the mfc ctrl sp i is the same as the pd i sp i interface (see section 5.1.1 ) the addresses for register access are calculated using the register number and the byte number in each register. to calculate the address, the register number is shifted left by 4 bits and the byte number is added as the 4 lowest bits. access using the 3 byte addressing mode is possible, and can be used when 2 byte mode is not imple- mented for the pd i sp i but since the highest bits of the address are always 0, accessing the mfc control sp i via 2 byte mode is su z cient. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 28 / 204 figure 13: mfc ctrl sp i 2 byte addressing figure 14: mfc ctrl sp i 3 byte addressing 5.2.2 timing example this example shows a generic mfc register read access with wait state. the delays between the transferred bytes are just to show the byte boundaries and are not required. figure 15: mfc sp i timing example 5.2.3 sharing bus lines with the pd i sp i to reduce the number of signals on the pcb or if the local application controller has only one sp i interface, the mfc ctrl sp i bus can share the sp i bus signals of the pd i sp i , requiring only separate chip select signals. i n this case, both interfaces are internally switched to the pd i sp i interface pins. the original mfc ctrl sp i signals (mos i , m i so, and sck) remain unconnected in this case. only the mfc_ctrl_sp i _csn pin/signal must be used if the mfc i o block is accessed. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com 6 6 6 6 tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 29 / 204 to share the sp i bus lines, con 1 guration pin pd i _shared_bus must be pulled high as shown in the 1 gure below. figure 16: sp i bus sharing ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 30 / 204 5.3 ethernet physical layer connection tmc8462 comes with two integrated 100-mbit ethernet phys eliminating the need for external phy components. the physical media interface can connect to (shielded) twisted pair copper buses ((s)tpc). port signals with index 0 represent the ethercat i n port. port signals with index 1 represent the ethercat out port. figure 17: physical bus interface pins tmc8462 pin description tnx negative pin of di ? erential transmit output pair tpx positive pin of di ? erential transmit output pair rnx negative pin of di ? erential receive output pair rpx positive pin of di ? erential receive output pair regoutx this is a regulator power output. a 10uf and 0.1uf should be connected to this pin for 1 ltering power noise. mclk phy con 1 guration clock output md i o phy con 1 guration data in-/output table 6: physical bus interface pin description ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 31 / 204 5.4 external circuitry and applications examples 5.4.1 device reset the nreset signal should at least be connected to vcc i o via a 10k resistor and to gnd via a 10nf capacitor if no other controlled reset source for proper power-on behavior and reset is used. tmc8462 nreset 10nf 10k vcc i o (3.3v) figure 18: minimum external circuit for power-on reset 5.4.2 supply filtering for pll supply the internal pll is supplied with the same 3.3v as used for vcc i o. an r/l/c 1 lter structure as shown in the circuit diagram is used. pllclk_gnd is connected to common ground. tmc8462 tstclk_select vcc i o (3.3v) pllclk_gnd pllclk_vcc i o 100nf 1 600 @100mhz vcc i o (3.3v) figure 19: pll supply 1 lter ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 32 / 204 5.4.3 phy power regulator filtering the internal phy circuits require external 1 lter capacitors. tmc8462 regout0 100nf 10f regout1 100nf 10f figure 20: phy power regulator 1 ltering ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 33 / 204 5.4.4 external circuit for fixed switching regulator 0 switching regulator 0 is an internal buck switching regulator and generates a 1 xed 3.3v supply with approx- imately 500ma. this 3.3v supply shall be used to power vcc i o and pllclk_vcc i o. this regulator comes with an integrated schottky diode which minimizes part count, when an external 5v supply is available. this 3.3v can also be used to power other on-board devices, e.g., eeprom or leds. the 3.3v rail is available at switching regulator 0 output sw0. more information on the switching regulators is given in section 7.21 . tmc8462 gnd_d i ode gnd0 sw_d i ode sw0 22h 22f + 47f 3.3v out vs0 vs=5v figure 21: external circuit for switching regulator 0 with vs0 = 5v tmc8462 gnd_d i ode gnd0 sw_d i ode sw0 22h 22f mss1p6 + 47f 3.3v out vs0 vs>5v figure 22: external circuit for switching regulator 0 with vs0 > 5v ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 34 / 204 5.4.5 external circuit for adjustable switching regulator 1 switching regulator 1 is an internal buck switching regulator and generates an adjustable supply rail with approximately 500ma. the voltage at sw1 can be adjusted using a resistor network in the switching regulator s feedback path at vout_fb. vout_fb should be at 1.2v using a resistor divider. sw1 can be used to power the high voltage i os using v i o1, v i o2, v i o3 as well as switching regulator 0 input vs0 (which generates a 1 xed 3.3v rail). sw1 can also be used to power other peripheral devices, e.g., hall signals of a bldc motor or external encoders. more information on the switching regulators is given in section 7.21 . gnd1 tmc8462 sw1 22h 22f mss1p6 + 47f 4.7k 100k vout_fb vout adj. out vs1 vs figure 23: external circuit for adjustable buck regulator ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 35 / 204 5.4.6 minimum external supply circuit for single 3.3v supply the diagram shows the minimum external circuit when using a single 3.3v supply only. both internal switching regulators are not used in this example. therefore, both supply ports vs0 and vs1 are not connected. the high voltage i os are also not used in this example. therefore, the three high voltage i o supply ports v i o1, v i o2, and v i o3 are not connected. tmc8462 supply vs 100nf vs0 vs1 4x vcc i o 4x100nf pllclk_vcc i o 100nf 1 600 @100mhz vs=3.3v vdd1v8_out 100nf 1.8v 4x vcc_core 4x100nf v i o1/2/3 vdd5_out vs=3.3v sw1 vout vout_fb gnd1 sw0 sw_d i ode gnd_d i ode gnd0 10x gnd pllclk_gnd gnd i o1/2/3 figure 24: minimum external supply circuit for single 3.3v supply ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 36 / 204 5.4.7 minimum external supply circuit for single 5v supply the diagram shows the minimum external circuit when using a single 5v supply only. switching regulator 0 is used to generate the 3.3v for vcc i o and pllclk_vcc i o. switching regulator 1 is not used in this example. therefore, supply port vs1 is not connected. the high voltage i os are also not used in this example. therefore, the three high voltage i o supply ports v i o1, v i o2, and v i o3 are not connected. tmc8462 supply vs 100nf vs0 vs=5v 100nf vs1 4x vcc i o 4x100nf pllclk_vcc i o 100nf 1 600 @100mhz 3.3v vdd1v8_out 100nf 1.8v 4x vcc_core 4x100nf v i o1/2/3 vdd5_out 100nf sw1 vout vout_fb gnd1 sw0 22h 22f + 47f 3.3v sw_d i ode gnd_d i ode gnd0 10x gnd pllclk_gnd gnd i o1/2/3 figure 25: minimum external supply circuit for single 5v supply ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 37 / 204 5.4.8 minimum external supply circuit for single supply >5v to connect tmc8462 to a single supply greater than 5v the circuit is very similar to figure 25 . the main di ? erence is that an additional external diode (mss1p6) is required at output sw0. the pin sw_d i ode is open. tmc8462 supply vs 100nf vs0 vs>5v 100nf vs1 4x vcc i o 4x100nf pllclk_vcc i o 100nf 1 600 @100mhz 3.3v vdd1v8_out 100nf 1.8v 4x vcc_core 4x100nf v i o1/2/3 vdd5_out 100nf sw1 vout vout_fb gnd1 sw0 22h 22f + 47f mss1p6 3.3v sw_d i ode gnd_d i ode gnd0 10x gnd pllclk_gnd gnd i o1/2/3 figure 26: minimum external supply circuit for single supply >5v ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 38 / 204 5.4.9 typical power supply chain using both buck converters vs 5v : : : 24v vs, vs1, v i o1, v i o2, v i o3 adj. buck converter 5v : : : 24v, tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 40 / 204 6 ethercat slave controller description 6.1 general ethercat i nformation tmc8462 contains a standard-conform ethercat slave controller (esc) providing real-time ethercat mac layer functionality to ethercat slave devices. the esc part of tmc8462 provides the following ethercat-related features: ? 16 kbyte of process data ram (pdram): the pdram is a dual ported ram, which allows exchange of data between the ethercat master and the local application. ? eight sync managers (sm): sync managers are used to control and secure the data exchange via the pdram in terms of data consistency, data security, and synchronized read/write operations on the data objects. two modes C bu ? ered mode and mailbox mode C are available. ? eight fieldbus memory management units (fmmu): fmmus are used for mapping of logical addresses to physical addresses. the ethercat master uses logical addressing for data than spans multiple slaves. an fmmu can map such a logical address range to a continuous local physical address range. ? 64 bit distributed clock support (dc): dc is the base of the real-time capability of ethercat. their underlying algorithms compute delay times between the master and the slaves and between slaves and update a common time stamp in all slaves. this way, synchronized time stamps (latch0/1) and synchronized trigger signals (sync0/1) are available in every slave and to the master. ? ii c interface for external s ii eeprom for esc con 1 guration: after reset and at power up, the esc requires reading basic (and advanced) con 1 guration data from an external s ii eeprom to properly con 1 gure interfaces, operation modes, and and feature availability. the s ii eeprom may be read and written by the master or the local application controller as well. ? sp i process data i nterface (pd i ): the pd i is the interface between the local application controller and the esc. application-speci 1 c process data and ethercat control and status information for the ethercat state machine (esm) is exchanged via this interface. ? device emulation mode: this mode is a special mode of operation where no esm in the application controller is required. the slave s operation states are simply directly set by the master without control of an esm. this is bene 1 cial for small and simple slaves, for example simple i o devices. to manufacture own slaves devices, a registration with the ethercat technology group (etg) is required. more information and resources on the ethercat technology and the ethercat standard are available here: ? ethercat technology group (etg) ( http://www.ethercat.org/ ) ? ethercat is standardized by the i ec ( http://www.iec.ch/ ) and 1 led as i ec-standard 61158. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 41 / 204 6.2 overview of available chip features the following table shows ethercat chip features available in tr i nam i c s ethercat slave controller solu- tions. chip feature / description domain tmc8460 tmc8461 tmc8462 tmc8670 extended dl control register 0x0102:0x0103 enabled register 1 1 1 1 al status code register 0x0134:0x0135 enabled register 1 1 1 1 ecat interrupt mask 0x0200:0x0201 enabled register 1 1 1 1 con 1 gured station alias 0x0012:0x0013 enabled register 1 1 1 1 general purpose inputs 0x0f18:0x0f1f enabled register 0 0 0 0 general purpose outputs 0x0f10:0x0f17 enabled register 0 0 0 0 al event mask 0x0204:0x0207 enabled register 1 1 1 1 physical rd/wr o ? set 0x0108:0x0109 enabled register 0 1 1 0 bridge port pd i ( 0x07 ) enabled register 0 0 0 0 writable watchdog divider 0x0400:0x0401 and watchdog pd i 0x0410:0x0411 enabled watchdog 1 1 1 0 watchdog counters 0x0442:0x0444 enabled watchdog 1 1 1 1 ecat write protection 0x0020:0x0031 enabled ext. function 0 1 1 0 reset registers 0x0040:0x0041 enabled ext. function 1 1 1 1 fpga update at 0x0e00 enabled ext. function 0 0 0 0 dc sync event times enabled ext. function 1 1 1 0 ecat processing unit and pd i error counters/pd i error code 0x030c:0x030e enabled ext. function 1 1 1 0 user ram disabled ext. functions 1 0 0 0 1: por values, 0: vendor i d ext. functions 0 0 0 0 eeprom control by pd i enabled phy layer 0 0 0 0 lost link counters 0x0310:0x0313 enabled phy layer 1 1 1 0 m ii management interface 0x0510 enabled phy layer 1 1 1 1 enhanced link detection for m ii enabled phy layer 1 1 1 1 link detection and con 1 guration for m ii enabled phy layer 0 1 1 0 pd i support for m ii management interface enabled phy layer 1 1 1 1 automatic m ii tx shift enabled phy layer 1 1 1 1 extended rx error counter registers 0x0314:0x0317 and 0x0320:0x0327 enabled phy layer 0 0 0 0 run led enabled leds 1 1 1 1 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 42 / 204 chip feature / description domain tmc8460 tmc8461 tmc8462 tmc8670 link/activity leds enabled leds 1 1 1 1 port error leds enabled leds 0 0 0 0 run/err led override registers 0x0138:0x0139 enabled leds 0 1 1 1 con 1 gurable sp i pd i modes enabled pd i 1 1 1 1 digital i o output register 0x0f00:0x0f03 disabled pd i 0 0 0 0 pd i user mode registers 0x0158/0x015c enabled pd i 0 0 0 0 dc latch unit enabled dc 1 1 1 1 external dc speed counter di ? direct control register 0x0938 enabled dc 0 0 0 0 dc sync unit enabled dc 1 1 1 1 dc time loop control by pd i enabled dc 0 0 0 0 dc with external local clock enabled dc 0 0 0 0 eeprom emulation enabled eeprom 0 0 0 0 removable pd i (socket communication) enabled eeprom 0 0 0 0 eeprom ram/rom instead of i 2c/emulation enabled eeprom 0 0 0 0 parameter loading to 0x0580 enabled eeprom 1 1 1 1 eeprom streaming support enabled eeprom 0 0 0 0 8 byte eeprom read data enabled eeprom 1 0 0 0 con 1 gurable eeprom s i ze enabled eeprom 1 1 1 1 extended esc con 1 guration register 0x0142:0x0143 (eeprom word 5) enabled eeprom 0 0 0 0 table 7: available ethercat chip features (0 = not available/disabled, 1 = available/enabled ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 43 / 204 6.3 ethercat register overview tmc8462 has an address space of 20 kbyte. the 1 rst block of 4kbyte ( 0x0000:0x0fff ) is reserved for the standard esc- and ethercat-relevant con 1 guration and status registers. the process data ram (pdram) starts at address 0x1000 . tmc8462 has a process data ram of 16 kbyte. address length (byte) description esc i nformation 0x0000 1 type 0x0001 1 revision 0x0002:0x0003 2 build 0x0004 1 fmmus supported 0x0005 1 syncmanagers supported 0x0006 1 ram size 0x0007 1 port descriptor 0x0008:0x0009 2 esc features supported station address 0x0010:0x0011 2 con 1 gured station address 0x0012:0x0013 2 con 1 gured station alias write protection 0x0020 1 write register enable 0x0021 1 write register protection 0x0030 1 esc write enable 0x0031 1 esc write protection data link layer 0x0040 1 esc reset ecat 0x0041 1 esc reset pd i 0x0100:0x0103 4 esc dl control 0x0108:0x0109 2 physical read/write o ? set 0x0110:0x0111 2 esc dl status ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 44 / 204 address length (byte) description application layer 0x0120:0x0121 2 al control 0x0130:0x0131 2 al status 0x0134:0x0135 2 al status code 0x0138 1 run led override 0x0139 1 err led override pd i 0x0140 1 pd i control 0x0141 1 esc con 1 guration 0x014e:0x014f 1 pd i i nformation 0x0150 4 pd i sp i slave con 1 guration 0x0151 4 sync/latch pd i con 1 guration 0x0152:0x0153 4 extended pd i sp i slave con 1 guration i nterrupts 0x0200:0x0201 2 ecat event mask 0x0204:0x0207 4 al event mask 0x0210:0x0211 2 ecat event request 0x0220:0x0223 4 al event request error counters 0x0300:0x0307 4x2 rx error counter[3:0] 0x0308:0x030b 4x1 forward rx error counter[3:0] 0x030c 1 ecat processing unit error counter 0x030d 1 pd i error counter 0x030e 1 pd i error code 0x0310:0x0313 4x1 lost link counter[3:0] ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 45 / 204 address length (byte) description watchdogs 0x0400:0x0401 2 watchdog divider 0x0410:0x0411 2 watchdog time pd i 0x0420:0x0421 2 watchdog time process data 0x0440:0x0441 2 watchdog status process data 0x0442 1 watchdog counter process data 0x0443 1 watchdog counter pd i s ii eeprom i nterface 0x0500 1 eeprom con 1 guration 0x0501 1 eeprom pd i access state 0x0502:0x0503 2 eeprom control/status 0x0504:0x0507 4 eeprom address 0x0508:0x050f 4/8 eeprom data m ii management i nterface 0x0510:0x0511 2 m ii management control/status 0x0512 1 phy address 0x0513 1 phy register address 0x0514:0x0515 2 phy data 0x0516 1 m ii management ecat access state 0x0517 1 m ii management pd i access state 0x0518:0x051b 4 phy port status 0x0580:0x05ff 128 esc parameter ram 0x0580:0x05ff 128 max. tmc8xxx mfc i o block con 1 guration ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 46 / 204 address length (byte) description 0x0600:0x06ff 16x16 fmmu[15:0] +0x0:0x3 4 logical start address +0x4:0x5 2 length +0x6 1 logical start bit +0x7 1 logical stop bit +0x8:0x9 2 physical start address +0xa 1 physical start bit +0xb 1 type +0xc 1 activate +0xd:0xf 3 reserved 0x0800:0x087f 16x8 syncmanager[15:0] +0x0:0x1 2 physical start address +0x2:0x3 2 length +0x4 1 control register +0x5 1 status register +0x6 1 activate +0x7 1 pd i control 0x0900:0x09ff distributed clocks (dc) dc receive times 0x0900:0x0903 4 receive time port 0 0x0904:0x0907 4 receive time port 1 0x0908:0x090b 4 receive time port 2 0x090c:0x090f 4 receive time port 3 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 47 / 204 address length (byte) description dc time loop control unit 0x0910:0x0917 4/8 system time 0x0918:0x091f 4/8 receive time ecat processing unit 0x0920:0x0927 4/8 system time o ? set 0x0928:0x092b 4 system time delay 0x092c:0x092f 4 system time di ? erence 0x0930:0x0931 2 speed counter start 0x0932:0x0933 2 speed counter di ? 0x0934 1 system time di ? erence filter depth 0x0935 1 speed counter filter depth dc cyclic unit control 0x0980 1 cyclic unit control dc sync out unit 0x0981 1 activation 0x0982:0x0983 2 pulse length of sync signals 0x0984 1 activation status 0x098e 1 sync0 status 0x098f 1 sync1 status 0x0990:0x0997 4/8 start time cyclic operation / next sync0 pulse 0x0998:0x099f 4/8 next sync1 pulse 0x09a0:0x09a3 4 sync0 cycle time 0x09a4:0x09a7 4 sync1 cycle time ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 48 / 204 address length (byte) description dc latch i n unit 0x09a8 1 latch0 control 0x09a9 1 latch1 control 0x09ae 1 latch0 status 0x09af 1 latch1 status 0x09b0:0x09b7 4/8 latch0 time positive edge 0x09b8:0x09bf 4/8 latch0 time negative edge 0x09c0:0x09c7 4/8 latch1 time positive edge 0x09c8:0x09cf 4/8 latch1 time negative edge dc syncmanager event times 0x09f0:0x09f3 4 ethercat bu ? er change event time 0x09f8:0x09fb 4 pd i bu ? er start event time 0x09fc:0x09ff 4 pd i bu ? er change event time 0x0e00:0x0eff 256 esc speci 1 c 0x0e00:0x0e07 8 product i d 0x0e08:0x0e0f 8 vendor i d 0x0f80:0x0fff 128 user ram 0x0f80:0x0fff 20 reserved process data ram 0x1000:0xffff 1-60kb process data ram table 8: tmc8462 ethercat registers for registers longer than one byte, the lsb has the lowest and msb the highest address. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 49 / 204 6.4 ethercat register set 6.4.1 esc i nformation 6.4.1.1 type ( 0x0000 ) bit description ecat pd i reset value 7:0 type of ethercat controller r/- r/- tmc8460: 0xd0 tmc8461: 0xd0 tmc8462: 0xd0 tmc8670: 0xd0 table 9: register 0x0000 (type) 6.4.1.2 revision ( 0x0001 ) bit description ecat pd i reset value 7:0 revision of ethercat controller r/- r/- tmc8460: 0x60 tmc8461: 0x61 tmc8462: 0x61 tmc8670: 0x70 table 10: register 0x0001 (revision) 6.4.1.3 build ( 0x0002:0x0003 ) bit description ecat pd i reset value 15:0 actual build of ethercat controller, minor version, maintenance version r/- r/- tmc8460: 0x10 tmc8461: 0x11 tmc8462: 0x11 tmc8670: 0x10 table 11: register 0x0002 (build) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 50 / 204 6.4.1.4 fmmus supported ( 0x0004 ) bit description ecat pd i reset value 7:0 number of supported fmmu channels (or enti- ties) of the ethercat slave controlller. r/- r/- tmc8460: 6 tmc8461: 8 tmc8462: 8 tmc8670: 3 table 12: register 0x0004 (fmmus) 6.4.1.5 syncmanagers supported ( 0x0005 ) bit description ecat pd i reset value 7:0 number of supported syncmanager channels (or entities) of the ethercat slave controller r/- r/- tmc8460: 6 tmc8461: 8 tmc8462: 8 tmc8670: 4 table 13: register 0x0005 (sms) 6.4.1.6 ram size ( 0x0006 ) bit description ecat pd i reset value 7:0 process data ram size supported by the ether- cat slave controller in kbyte r/- r/- tmc8460: 16 tmc8461: 16 tmc8462: 16 tmc8670: 4 table 14: register 0x0006 (ram size) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 51 / 204 6.4.1.7 port descriptor ( 0x0007 ) bit description ecat pd i reset value port con 1 guration: 00: not implemented 01: not con 1 gured (s ii eeprom) 10: ebus 11: m ii rm ii rgm ii 1:0 port 0 r/- r/- tmc8460: 11 tmc8461: 11 tmc8462: 11 tmc8670: 11 3:2 port 1 r/- r/- tmc8460: 11 tmc8461: 11 tmc8462: 11 tmc8670: 11 7:4 not supported r/- r/- 0 table 15: register 0x0007 (port descriptor) 6.4.1.8 esc features supported ( 0x0008:0x0009 ) bit description ecat pd i reset value 0 fmmu operation: 0: bit oriented 1: byte oriented r/- r/- 1 reserved r/- r/- 2 distributed clocks: 0: not available 1: available r/- r/- 3 distributed clocks (width): 0: 32 bit 1: 64 bit r/- r/- 4 low jitter ebus: 0: not available, standard jitter 1: available, jitter minimized r/- r/- 0 5 enhanced link detection ebus: 0: not available 1: available r/- r/- 0 6 enhanced link detection m ii 0: not available 1: available r/- r/- ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 52 / 204 bit description ecat pd i reset value 7 separate handling of fcs errors: 0: not supported 1: supported, frames with wrong fcs and ad- ditional nibble will be counted separately in forwarded rx error counter r/- r/- 8 enhanced dcsync activation 0: not available 1: available note: this feature refers to registers 0x981.(7:3) , 0x0984 r/- r/- 9 ethercat lrw command support: 0: supported 1: not supported r/- r/- 10 ethercat read/write command support 0: supported 1: not supported r/- r/- 11 fixed fmmu/syncmanager con 1 guration 0: variable con 1 guration 1: fixed con 1 guration (refer to documentation of supporting escs) r/- r/- 15:12 reserved r/- r/- table 16: register 0x0008:0x0009 (esc features) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 53 / 204 6.4.2 station address 6.4.2.1 con 1 gured station address ( 0x0010:0x0011 ) bit description ecat pd i reset value 15:0 address used for node addressing (fpxx com- mands) r/w r/- table 17: register 0x0010:0x0011 (station addr) 6.4.2.2 con 1 gured station alias ( 0x0012:0x0013 ) bit description ecat pd i reset value 15:0 alias address used for node addressing (fpxx commands) the use of this alias is activated by register dl control bit 24 ( 0x0100.24 / 0x0103.0 ) note: eeprom value is only taken over at 1 rst eeprom load after power- on reset. r/- r/w table 18: register 0x0012:0x0013 (station alias) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 54 / 204 6.4.3 write protection 6.4.3.1 write register enable ( 0x0020 ) bit description ecat pd i reset value 0 i f write register protection is enabled, this reg- ister has to be written in the same ethernet frame (value does not care) before other writes to this station are allowed. write protection is still active after this frame (if write register protection register is not changed). r/w r/- 7:1 reserved, wirte 0 r/- r/- table 19: register 0x0020 (write register enable) 6.4.3.2 write register protection ( 0x0021 ) bit description ecat pd i reset value 0 write register protection: 0: protection disabled 1: protection enabled registers 0x0000-0x0137 , 0x013a-0x0f0f are write protected, except for 0x0030 r/w r/- 7:1 reserved, write 0 r/- r/- table 20: register 0x0021 (write register prot.) 6.4.3.3 esc write enable ( 0x0030 ) bit description ecat pd i reset value 0 i f esc write protection is enabled, this register has to be written in the same ethernet frame (value does not care) before other writes to this station are allowed. esc write protection is still active after this frame (if esc write protection register is not changed). r/w r/- 7:1 reserved, write 0 r/- r/- table 21: register 0x0030 (esc write enable) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 55 / 204 6.4.3.4 esc write protection ( 0x0031 ) bit description ecat pd i reset value 15:0 write protect: 0: protection disabled 1: protection enabled all areas are write protected, except for 0x0030 . r/w r/- 7:1 reserved, write 0 r/- r/- table 22: register 0x0031 (esc write prot.) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 56 / 204 6.4.4 data link layer 6.4.4.1 esc reset ecat ( 0x0040 ) bit description ecat pd i reset value write 7:0 reset is asserted after writing 0x52 ( r ), 0x45 ( e ), 0x53 ( s ) in this register with 3 consecutive frames. r/w r/- read 1:0 progress of the reset procedure: 01: after writing 0x52 10: after writing 0x45 (if 0x52 was written) 00: else r/w r/- 7:2 reserved, write 0 r/- r/- table 23: register 0x0040 (esc reset ecat) 6.4.4.2 esc reset pd i ( 0x0041 ) bit description ecat pd i reset value write 7:0 reset is asserted after writing 0x52 ( r ), 0x45 ( e ), 0x53 ( s ) in this register with 3 consecutive commands. r/- r/w read 1:0 progress of the reset procedure: 01: after writing 0x52 10: after writing 0x45 (if 0x52 was written) 00: else r/- r/w 7:2 reserved, write 0 r/- r/- table 24: register 0x0041 (esc reset pd i ) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 57 / 204 6.4.4.3 esc dl control ( 0x0100:0x0103 ) bit description ecat pd i reset value 0 forwarding rule: 0: ethercat frames are processed, non-ethercat frames are forwarded without processing 1: ethercat frames are processed, non- ethercat frames are destroyed the source mac address is changed for every frame (source_mac[1] is set to 1 - locally ad- ministered address) regardless of the forward- ing rule. r/- r/- 1 temporary use of settings in register 0x101 : 0: permanent use 1: use for about 1 second, then revert to previ- ous settings r/- r/- 7:2 reserved, write 0 r/- r/- 9:8 loop port 0: 00: auto 01: auto close 10: open 11: closed note loop open means sending/receiving over this port is enabled, loop closed means send- ing/receiving is disabled and frames are for- warded to the next open port internally. auto: loop closed at link down, opened at link up auto close: loop closed at link down, opened with writing 01 again after link up (or receiving a valid ethernet frame at the closed port) open: loop open regardless of link state closed: loop closed regardless of link state r/w* r/- 11:10 loop port 1: 00: auto 01: auto close 10: open 11: closed r/w* r/- 13:12 loop port 2: 00: auto 01: auto close 10: open 11: closed r/w* r/- 15:14 loop port 3: 00: auto 01: auto close 10: open 11: closed r/w* r/- ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 58 / 204 bit description ecat pd i reset value 18:16 rx f i fo size (esc delays start of forwarding until f i fo is at least half full). rx f i fo size/rx delay reduction** : value (for m ii ): 0: -40 ns 1: -40 ns 2: -40 ns 3: -40 ns 4: no change 5: no change 6: no change 7: default default note: eeprom value is only taken over at 1 rst eeprom load after power-on or reset r/w r/- 19 ebus low jitter: 0: normal jitter / 1: reduced jitter r/w r/- 0 21:20 reserved, write 0 r/w r/- 22 ebus remote link down signaling time: 0: default ( 660 ms) 1: reduced ( 80 s) r/w r/- 0 23 reserved, write 0 r/w r/- 24 station alias: 0: i gnore station alias 1: alias can be used for all con 1 gured address command types (fprd, fpwr, . . . ) r/w r/- 31:25 reserved, write 0 r/- r/- table 25: register 0x0100:0x0103 (dl control) * loop con 1 guration changes are delayed until end of currently received or transmitted frame at the port. ** the possibility of rx f i fo size reduction depends on the clock source accuracy of the esc and of every connected ethercat/ethernet devices (master, slave, etc.). rx f i fo size of 7 is su z cient for 100ppm accuracy, f i fo size 0 is possible with 25ppm accuracy (frame size of 1518/1522 byte). 6.4.4.4 physical read/write o ? set ( 0x0108:0x0109 ) bit description ecat pd i reset value 15:0 o ? set of r/w commands (fprw, aprw) between read address and write address. rd_adr = adr and wr_adr = adr + r/w- o ? set 0 r/w r/- table 26: register 0x0108:0x0109 (r/w o ? set) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 59 / 204 6.4.4.5 esc dl status ( 0x0110:0x0111 ) bit description ecat pd i reset value 0 pd i operational/eeprom loaded correctly: 0: eeprom not loaded, pd i not operational (no access to process data ram) 1: eeprom loaded correctly, pd i operational (access to process data ram) r*/- r/- 1 pd i watchdog status: 0: watchdog expired 1: watchdog reloaded r*/- r/- 2 enhanced link detection: 0: deactivated for all ports 1: activated for at least one port note: eeprom value is only taken over at 1 rst eeprom load after power-on or reset r*/- r/- 3 reserved r*/- r/- 4 physical link on port 0: 0: no link 1: link detected r*/- r/- 5 physical link on port 1: 0: no link 1: link detected r*/- r/- 6 physical link on port 2: 0: no link 1: link detected r*/- r/- 7 physical link on port 3: 0: no link 1: link detected r*/- r/- 8 loop port 0: 0: open 1: closed r*/- r/- 9 communication on port 0: 0: no stable communication 1: communication established r*/- r/- 10 loop port 1: 0: open 1: closed r*/- r/- 11 communication on port 1: 0: no stable communication 1: communication established r*/- r/- 12 loop port 2: 0: open 1: closed r*/- r/- 13 communication on port 2: 0: no stable communication 1: communication established r*/- r/- ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 60 / 204 bit description ecat pd i reset value 14 loop port 3: 0: open 1: closed r*/- r/- 15 communication on port 3: 0: no stable communication 1: communication established r*/- r/- table 27: register 0x0110:0x0111 (dl status) * reading dl status register from ecat clears ecat event request 0x0210.2 . register 0x0111 port 3 port2 port1 port 0 0x55 no link, closed no link, closed no link, closed no link, closed 0x56 no link, closed no link, closed no link, closed link, open 0x59 no link, closed no link, closed link, open no link, closed 0x5a no link, closed no link, closed link, open link, open 0x65 no link, closed link, open no link, closed no link, closed 0x66 no link, closed link, open no link, closed link, open 0x69 no link, closed link, open link, open no link, closed 0x6a no link, closed link, open link, open link, open 0x95 link, open no link, closed no link, closed no link, closed 0x96 link, open no link, closed no link, closed link, open 0x99 link, open no link, closed link, open no link, closed 0x9a link, open no link, closed link, open link, open 0xa5 link, open link, open no link, closed no link, closed 0xa6 link, open link, open no link, closed link, open 0xa9 link, open link, open link, open no link, closed 0xaa link, open link, open link, open link, open 0xd5 link, closed no link, closed no link, closed no link, closed 0xd6 link, closed no link, closed no link, closed link, open 0xd9 link, closed no link, closed link, open no link, closed 0xda link, closed no link, closed link, open link, open table 28: decoding port state in esc dl status register 0x0111 (typical modes only) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 61 / 204 6.4.5 application layer 6.4.5.1 al control ( 0x0120:0x0121 ) bit description ecat pd i reset value 3:0 i nitiate state transition of the device state ma- chine: 1: request i nit state 3: request bootstrap state 2: request pre-operational state 4: request safe-operational state 8: request operational state r/(w) r/ (wack)* 4 error i nd ack: 0: no ack of error i nd in al status register 1: ack of error i nd in al status register r/(w) r/ (wack)* 4 device i denti 1 cation: 0: no request 1: device i denti 1 cation request r/(w) r/ (wack)* 15:6 reserved, write 0 r/(w) r/ (wack)* table 29: register 0x0120:0x0121 (al cntrl) note al control register behaves like a mailbox if device emulation is o ? ( 0x0140.8 =0): the pd i has to read/write* the al control register after ecat has written it. otherwise ecat cannot write again to the al control register. after reset, al control register can be written by ecat. (regarding mailbox functionality, both registers 0x0120 and 0x0121 are equivalent, e.g. reading 0x0121 is su z cient to make this register writeable again.) i f device emulation is on, the al control register can always be written, its content is copied to the al status register. * pd i register function acknowledge by write command is disabled: reading al control from pd i clears al event request 0x0220.0 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing al control from pd i clears al event request 0x0220.0 . writing to this register from pd i is possible; write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 62 / 204 6.4.5.2 al status ( 0x0130:0x0131 ) bit description ecat pd i reset value 3:0 actual state of the device state machine: 1: i nit state 3: request bootstrap state 2: pre-operational state 4: safe-operational state 8: operational state r*/- r/(w) 4 error i nd: 0: device is in state as requested or flag cleared by command 1: device has not entered requested state or changed state as result of a local action r*/- r/(w) 5 device i denti 1 cation: 0: device i denti 1 cation not valid 1: device i denti 1 cation loaded r*/- r/(w) 15:6 reserved, write 0 r*/- r/(w) table 30: register 0x0130:0x0131 (al status) note al status register is only writable from pd i if device emulation is o ? ( 0x0140.8 =0), otherwise al status register will re 2 ect al control register values. * reading al status from ecat clears ecat event request 0x0210.3 . 6.4.5.3 al status code ( 0x0134:0x0135 ) bit description ecat pd i reset value 15:0 al status code r/- r/w table 31: register 0x0134:0x0135 (al status code) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 63 / 204 6.4.5.4 run led override ( 0x0138 ) bit description ecat pd i reset value 3:0 led code: (fsm state) 0x0 : o ? (1- i nit) 0x1-0xc : flash 1x - 12x (4-safeop 1x) 0xd : blinking (2-preop) 0xe : flickering (3-bootrap) 0xf : on r/w r/w 4 enable override: 0: override disabled 1: override enabled r/w r/w 7:5 reserved, write 0 r/w r/w table 32: register 0x0138 (run led override) note changes to al status register ( 0x0130 ) with valid values will disable run led override ( 0x0138.4 =0). the value read in this register always re 2 ects current led output. 6.4.5.5 err led override ( 0x0139 ) bit description ecat pd i reset value 3:0 led code: 0x0 : o ? 0x1-0xc : flash 1x - 12x 0xd : blinking 0xe : flickering 0xf : on r/w r/w 4 enable override: 0: override disabled 1: override enabled r/w r/w 7:5 reserved, write 0 r/w r/w table 33: register 0x0139 (err led override) note new error conditions will disable err led override ( 0x0139.4 =0). the value read in this register always re 2 ects current led output. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 64 / 204 6.4.6 pd i 6.4.6.1 pd i control ( 0x0140 ) bit description ecat pd i reset value 7:0 process data interface: 0x00 : i nterface deactivated (no pd i ) . . . 0x05 : sp i slave . . . 0x80 : on-chip bus others: reserved r/- r/- tmc8460, tmc8461, tmc8462, tmc8670: 0x00 later eeprom adr 0x0000 only sp i slave ( 0x05 ) is supported in the hardware table 34: register 0x0140 (pd i control) 6.4.6.2 esc con 1 guration ( 0x0141 ) bit description ecat pd i reset value 0 device emulation (control of al status): 0: al status register has to be set by pd i 1: al status register will be set to value written to al control register r/w r/- 1 enhanced link detection all ports: 0: disabled (if bits [7:4]=0) 1: enabled at all ports (overrides bits [7:4]) r/- r/- 2 distributed clocks sync out unit: 0: disabled (power saving) / 1: enabled r/- r/- 3 distributed clocks latch i n unit: 0: disabled (power saving) / 1: enabled r/- r/- 4 enhanced link port 0: 0: disabled (if bit 1=0) / 1: enabled r/- r/- 5 enhanced link port 1: 0: disabled (if bit 1=0) / 1: enabled r/- r/- 6 enhanced link port 2: 0: disabled (if bit 1=0) / 1: enabled r/- r/- 7 enhanced link port 3: 0: disabled (if bit 1=0) / 1: enabled r/- r/- table 35: register 0x0141 (esc con 1 g) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 65 / 204 6.4.6.3 pd i i nformation ( 0x014e:0x014f ) bit description ecat pd i reset value 0 pd i register function acknowledge by write: 0: disabled 1: enabled r/w r/- depends on con 1 guration 1 pd i con 1 gured: 0: pd i not con 1 gured 1: pd i con 1 gured (eeprom loaded) r/w r/- 0 2 pd i active: 0: pd i not active 1: pd i active r/w r/- 0 3 pd i con 1 guration invalid: 0: pd i con 1 guration ok 1: pd i con 1 guration invalid r/w r/- 0 7:4 reserved r/w r/- 0 table 36: register 0x014e (pd i i nformation)) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 66 / 204 6.4.6.4 pd i sp i slave con 1 guration ( 0x0150 ) the pd i con 1 guration register 0x0150 and the extended pd i con 1 guration registers 0x0152:0x0153 depend on the selected pd i . the sync/latch[1:0] pd i con 1 guration register 0x0151 is independent of the selected pd i . the tmc8460, tmc8461, tmc8462, and tmc8670 devices support sp i slave pd i only. bit description ecat pd i reset value 1:0 sp i mode: 00: sp i mode 0 01: sp i mode 1 10: sp i mode 2 11: sp i mode 3 note: sp i mode 3 is recommended for slave sample code note: sp i status 2 ag is not available in sp i modes 0 and 2 with normal data out sample. r/- r/- 3:2 sp i _ i rq output driver/polarity: 00: push-pull active low 01: open drain (active low) 10: push-pull active high 11: open source (active high) r/- r/- 4 sp i _csnl polarity: 0: active low 1: active high r/- r/- 5 data out sample mode: 0: normal sample (sp i _m i so and sp i _mos i are sampled at the same sp i _clk edge) 1: late sample (sp i _m i so and sp i _mos i are sampled at di ? erent sp i _clk edges) r/- r/- 7:6 reserved, set eeprom value 0 r/- r/- table 37: register 0x0150 (pd i sp i cfg) 6.4.6.5 sync/latch con 1 guration ( 0x0151 ) bit description ecat pd i reset value 1:0 sync0 output driver/polarity: 00: push-pull active low 01: open drain (active low) 10: push-pull active high 11: open source (active high) r/- r/- tmc8461: 10 tmc8462: 10 2 sync0/latch0 con 1 guration: 0: latch0 i nput 1: sync0 output r/- r/- tmc8461: 1 tmc8462: 1 3 sync0 mapped to al event request register 0x0220.2 : 0: disabled 1: enabled r/- r/- tmc8461, tmc8462: de- pends on con 1 guration ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 67 / 204 bit description ecat pd i reset value 5:4 sync1 output driver/polarity: 00: push-pull active low 01: open drain (active low) 10: push-pull active high 11: open source (active high) r/- r/- tmc8461: 10 tmc8462: 10 6 sync1/latch1 con 1 guration*: 0: latch1 input 1: sync1 output r/- r/- tmc8461: 1 tmc8462: 1 7 sync1 mapped to al event request register 0x0220.3 : 0: disabled 1: enabled r/- r/- tmc8461, tmc8462: de- pends on con 1 guration table 38: register 0x0151 (sync/latch cfg) 6.4.6.6 pd i sp i slave extended con 1 guration ( 0x0152:0x0153 ) bit description ecat pd i reset value 15:0 reserved, set eeprom value 0 r/- r/- tmc8461: 0 tmc8462: 0 table 39: register 0x0152:0x0153 (pd i sp i extcfg) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 68 / 204 6.4.7 i nterrupts 6.4.7.1 ecat event mask ( 0x0200:0x0201 ) bit description ecat pd i reset value 15:0 ecat event masking of the ecat event request events for mapping into ecat event 1 eld of ethercat frames: 0: corresponding ecat event request register bit is not mapped 1: corresponding ecat event request register bit is mapped r/w r/- table 40: register 0x0200:0x0201 (ecat event m.) 6.4.7.2 al event mask ( 0x0204:0x0207 ) bit description ecat pd i reset value 31:0 al event masking of the al event request reg- ister events for mapping to pd i i rq signal: 0: corresponding al event request register bit is not mapped 1: corresponding al event request register bit is mapped r/- r/w table 41: register 0x0204:0x0207 (al event mask) 6.4.7.3 ecat event request ( 0x0210:0x0211 ) bit description ecat pd i reset value 0 dc latch event: 0: no change on dc latch i nputs 1: at least one change on dc latch i nputs (bit is cleared by reading dc latch event times from ecat for ecat controlled latch units, so that latch 0/1 status 0x09ae:0x09af indicates no event) r/- r/- 1 reserved r/- r/- 2 dl status event: 0: no change in dl status 1: dl status change (bit is cleared by reading out dl status 0x0110:0x0111 from ecat) r/- r/- ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 69 / 204 bit description ecat pd i reset value 3 al status event: 0: no change in al status 1: al status change (bit is cleared by reading out al status 0x0130:0x0131 from ecat) r/- r/- 4 5 ... mirrors values of each syncmanager status: 0: no sync channel 0 event 1: sync channel 0 event pending 0: no sync channel 1 event 1: sync channel 1 event pending . . . 0: no sync channel 7 event 1: sync channel 7 event pending r/w r/- 15:12 reserved r/- r/- table 42: register 0x0210:0x0211 (ecat event r.) 6.4.7.4 al event request ( 0x0220:0x0223 ) bit description ecat pd i reset value 0 al control event: 0: no al control register change 1: al control register has been written 1 (bit is cleared by reading al control register 0x0120:0x0121 from pd i ) r/- r/- 1 dc latch event: 0: no change on dc latch i nputs 1: at least one change on dc latch i nputs (bit is cleared by reading dc latch event times from pd i , so that latch 0/1 status 0x09ae:0x09af indicates no event. available if latch unit is pd i controlled) r/- r/- 2 state of dc sync0 (if register 0x0151.3 =1): (bit is cleared by reading sync0 status 0x098e from pd i , use only in acknowledge mode) r/- r/- 3 state of dc sync1 (if register 0x0151.7 =1): (bit is cleared by reading of sync1 status 0x098f from pd i , use only in acknowledge mode) r/- r/- 1 al control event is only generated if pd i emulation is turned o ? (pd i control register 0x0140.8 =0) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 70 / 204 bit description ecat pd i reset value 4 syncmanager activation register (syncmanager register o ? set 0x6 ) changed: 0: no change in any syncmanager 1: at least one syncmanager changed (bit is cleared by reading syncmanager activa- tion registers 0x0806 etc. from pd i ) r/- r/- 5 eeprom emulation: 0: no command pending 1: eeprom command pending (bit is cleared by acknowledging the command in eeprom command register 0x0502 from pd i ) r/- r/- 6 watchdog process data: 0: has not expired 1: has expired (bit is cleared by reading watchdog status pro- cess data 0x0440 from pd i ) r/- r/- 7 reserved r/- r/- 8 9 ... 23 syncmanager interrupts (syncmanager register o ? set 0x5, bit [0] or [1]): 0: no syncmanager 0 interrupt 1: syncmanager 0 interrupt pending 0: no syncmanager 1 interrupt 1: syncmanager 1 interrupt pending . . . 0: no syncmanager 15 interrupt 1: syncmanager 15 interrupt pending r/- r/- 31:24 reserved r/- r/- table 43: register 0x0220:0x0223 (al event r.) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 71 / 204 6.4.8 error counters errors are only counted if the corresponding port is enabled. 6.4.8.1 rx error counter[3:0] ( 0x0300:0x0307 ) bit description ecat pd i reset value 7:0 i nvalid frame counter of port y (counting is stopped when 0xff is reached). r/ w(clr) r/- 15:8 rx error counter of port y (counting is stopped when 0xff is reached). this is coupled directly to rx err of m ii interface. r/ w(clr) r/- table 44: register 0x0300:0x0307 (rx err cnt) 6.4.8.2 forward rx error counter[3:0] ( 0x0308:0x030b ) bit description ecat pd i reset value 7:0 forwarded error counter of port y (counting is stopped when 0xff is reached). r/ w(clr) r/- table 45: register 0x0308:0x030b (fw rx err cnt) note error counters 0x0300 - 0x030b are cleared if one of the rx error counters 0x0300 - 0x030b is written. write value is ignored (write 0). 6.4.8.3 ecat processing unit error counter ( 0x030c ) bit description ecat pd i reset value 7:0 ecat processing unit error counter (counting is stopped when 0xff is reached). counts errors of frames passing the processing unit (e.g., fcs is wrong or datagram structure is wrong). r/ w(clr) r/- table 46: register 0x030c (proc. unit err cnt) note error counter 0x030c is cleared if error counter 0x030c is written. write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 72 / 204 6.4.8.4 pd i error counter ( 0x030d ) bit description ecat pd i reset value 7:0 pd i error counter (counting is stopped when 0xff is reached). counts if a pd i access has an interface error. r/ w(clr) r/- table 47: register 0x030d (pd i err cnt) note error counter 0x030d and error code 0x030e are cleared if error counter 0x030d is written. write value is ignored (write 0). 6.4.8.5 pd i error code ( 0x030e ) bit description ecat pd i reset value sp i access which caused last pd i error. cleared if register 0x030d is written. r/- r/- 2:0 number of sp i clock cycles of whole access (modulo 8) r/- r/- 3 busy violation during read access r/- r/- 4 read termination missing r/- r/- 5 access continued after read termination byte r/- r/- 7:6 sp i command cmd[2:1] r/- r/- table 48: register 0x030e (pd i err code) note error counter 0x030d and error code 0x030e are cleared if error counter 0x030d is written. write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 73 / 204 6.4.8.6 lost link counter[3:0] ( 0x0310:0x0313 ) bit description ecat pd i reset value 7:0 lost link counter of port y (counting is stopped when 0xff is reached). counts only if port loop is auto. r/w(clr) r/- table 49: register 0x0310:0x0313 (ll counter) note only lost links at open ports are counted. lost link counters 0x0310 - 0x0313 are cleared if one of the lost link counters 0x0310 - 0x0313 is written. write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 74 / 204 6.4.9 watchdogs 6.4.9.1 watchdog divider ( 0x0400:0x0401 ) bit description ecat pd i reset value 15:0 watchdog time pd i : number or basic watch- dog increments (default value with watchdog divider 100 s means 100ms watchdog) r/w r/- table 50: register 0x0400:0x0401 (wd divider) 6.4.9.2 watchdog time pd i ( 0x0410:0x0411 ) bit description ecat pd i reset value 15:0 watchdog time pd i : number or basic watch- dog increments (default value with watchdog divider 100 s means 100ms watchdog) r/w r/- table 51: register 0x0410:0x0411 (wd time pd i ) note watchdog is disabled if watchdog time is set to 0x0000 . watchdog is restarted with every pd i access. 6.4.9.3 watchdog time process data ( 0x0420:0x0421 ) bit description ecat pd i reset value 15:0 watchdog time process data: number of basic watchdog increments (default value with watchdog divider 100 s means 100ms watchdog) r/w r/- table 52: register 0x0420:0x0421 (wd time pd) note there is one watchdog for all syncmanagers. watchdog is disabled if watchdog time is set to 0x0000 . watchdog is restarted with every write access to syncman- agers with watchdog trigger enable bit set. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 75 / 204 6.4.9.4 watchdog status process data ( 0x0440:0x0441 ) bit description ecat pd i reset value 15:0 watchdog status of process data (triggered by syncmanagers) 0: watchdog process data expired 1: watchdog process data is active or disabled r/- r/ (w ack)* 0 reserved r/- r/ (w ack)* table 53: register 0x0440:0x0441 (wd status pd) * pd i register function acknowledge by write command is disabled: reading this register from pd i clears al event request 0x0220.6 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i clears al event request 0x0220.6 . writing to this register from pd i is possible; write value is ignored (write 0). 6.4.9.5 watchdog counter process data ( 0x0442 ) bit description ecat pd i reset value 7:0 watchdog counter process data (counting is stopped when 0xff is reached). counts if pro- cess data watchdog expires. r/ w(clr) r/- table 54: register 0x0442 (wd counter pd) note watchdog counters 0x0442 - 0x0443 are cleared if one of the watchdog counters 0x0442 - 0x0443 is written. write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 76 / 204 6.4.9.6 watchdog counter pd i ( 0x0443 ) bit description ecat pd i reset value 7:0 watchdog pd i counter (counting is stopped when 0xff is reached). counts if pd i watch- dog expires. r/ w(clr) r/- table 55: register 0x0443 (wd counter pd i ) note watchdog counters 0x0442 & 0x0443 are cleared if one of the watchdog counters 0x0442 & 0x0443 is written. write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 77 / 204 6.4.10 s ii eeprom i nterface address length (byte) description s ii eeprom i nterface 0x0500 1 eeprom con 1 guration 0x0501 1 eeprom pd i access state 0x0502:0x0503 2 eeprom control/status 0x0504:0x0507 4 eeprom address 0x0508:0x050f 4/8 eeprom data table 56: s ii eeprom i nterface register overview 6.4.10.1 eeprom con 1 guration ( 0x0500 ) bit description ecat pd i reset value 0 eeprom control is o ? ered to pd i : 0: no 1: yes (pd i has eeprom control) r/w r/- 1 force ecat access: 0: do not change bit 0x0501.0 1: reset bit 0x0501.0 to 0 r/w r/- 7:2 reserved, write 0 r/w r/- table 57: register 0x0500 (prom con 1 g) 6.4.10.2 eeprom pd i access state ( 0x0501 ) bit description ecat pd i reset value 0 access to eeprom: 0: pd i releases eeprom access 1: pd i takes eeprom access (pd i has eeprom control) r/- r/(w) 7:1 reserved, write 0 r/- r/- table 58: register 0x0501 (prom pd i access) note r/(w): write access is only possible if 0x0500.0 =1 and 0x0500.1 =0. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 78 / 204 6.4.10.3 eeprom control/status ( 0x0502:0x0503 ) bit description ecat pd i reset value 0 ecat write enable 2 : 0: write requests are disabled 1: write requests are enabled this bit is always 1 if pd i has eeprom control. r/(w) r/- 4:1 reserved, write 0 r/- r/- 5 eeprom emulation: 0: normal operation ( i 2c interface used) 1: pd i emulates eeprom ( i 2c not used) r/- r/- 6 supported number of eeprom read bytes: 0: 4 bytes 1: 8 bytes r/- r/- 7 selected eeprom algorithm: 0: 1 address byte (1kbit . . . 16kbit eeproms) 1: 2 address bytes (32kbit . . . 4 mbit eeproms) r/- r/- r/[w] 10:8 command register 1 : write: i nitiate command. read: currently executed command commands: 000: no command/eeprom idle (clear error bits) 001: read 010: write 100: reload others: reserved/invalid commands (do not issue) eeprom emulation only: after execution, pd i writes command value to indicate operation is ready. r/(w) r/(w) r/[w] 11 checksum error at in esc con 1 guration area: 0: checksum ok 1: checksum error r/- r/- 12 eeprom loading status: 0: eeprom loaded, device information ok 1: eeprom not loaded, device information not available (eeprom loading in progress or 1 n- ished with a failure) r/- r/- 13 error acknowledge/command 2 : 0: no error 1: missing eeprom acknowledge or invalid command eeprom emulation only: pd i writes 1 if a tem- porary failure has occurred. r/- r/- r/[w] ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 79 / 204 bit description ecat pd i reset value 14 error write enable 2 : 0: no error 1: write command without write enable r/- r/- 15 busy: 0: eeprom i nterface is idle 1: eeprom i nterface is busy r/- r/- table 59: register 0x0502:0x0503 (prom cntrl) note r/(w): write access depends upon the assignment of the eeprom interface (ecat/pd i ). write access is generally blocked if eeprom interface is busy ( 0x0502.15 =1). note r/[w]: eeprom emulation only: write access is possible if eeprom interface is busy ( 0x0502.15 =1). pd i acknowledges pending commands by writing a 1 into the corresponding command register bits ( 0x0502.10:8 ). errors can be indicated by writing a 1 into the error bit 0x0502.13 . acknowledging clears al event request 0x0220.5 . *1 write enable bit 0 is self-clearing at the sof of the next frame, command bits [10:8] are self-clearing after the command is executed (eeprom busy ends). writing " 000" to the command register will also clear the error bits [14:13]. command bits [10:8] are ignored if error acknowledge/command is pending (bit 13). *2 error bits are cleared by writing " 000" (or any valid command) to command register bits [10:8]. 6.4.10.4 eeprom address ( 0x0504:0x0507 ) bit description ecat pd i reset value 31:0 eeprom address 0: first word (= 16 bit) 1: second word . . . actually used eeprom address bits: [9:0]: eeprom size up to 16 kbit [17:0]: eeprom size 32 kbit . . . 4 mbit [32:0]: eeprom emulation r/(w) r/(w) table 60: register 0x0504:0x0507 (prom address) note r/(w): write access depends upon the assignment of the eeprom interface (ecat/pd i ). write access is generally blocked if eeprom interface is busy ( 0x0502.15 =1). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 80 / 204 6.4.10.5 eeprom data ( 0x0508:0x050f ) bit description ecat pd i reset value 15:0 eeprom write data (data to be written to eep- rom) or eeprom read data (data read from eeprom,. lower bytes) r/(w) r/[w] 63:16 eeprom read data (data read from eeprom, higher bytes) r/- r/- r[w] table 61: register 0x0508:0x050f (prom data) note r/(w): write access depends upon the assignment of the eeprom interface (ecat/pd i ). write access is generally blocked if eeprom interface is busy ( 0x0502.15 =1). note r/[w]: write access for eeprom emulation if read or reload command is pending. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 81 / 204 6.4.11 esc parameter ram 6.4.11.1 mfc i o block con 1 guration ( 0x0580:0x05e1 ) byte description ecat pd i reset value bytes 96...0 mfc i o block con 1 guration vector for - crossbar mapping and i o signal assignment - high voltage i o (hv i o) con 1 guration - switching regulator con 1 guration - memory block mapping - and mfc i o block register con 1 guration r/w r/w table 62: register 0x0580:0x05e1 (mfc i o con 1 g) the content of this address block in the esc parameter ram can be automatically loaded from the s ii eep- rom after reset/power-up as a con 1 guration vector that is written to addresses 0x0580:0x05e1 in the esc s memory space. the respective data in the s ii eeprom must be of category 1! nevertheless, mfc i o con 1 guration data can also be written and updated online by the ethercat master via the ecat interface or from a local application controller via the pd i interface by directly accessing addresses 0x0580:0x05e1 in the esc s memory space. more information on the individual con 1 guration bytes in this con 1 guration vector is given in section 7.4 C s ii eeprom mfc i o block parameter map and its following sections. example con 1 gurations are given in section 7.10 . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 82 / 204 6.4.12 m ii management i nterface address length (byte) description m ii management i nterface 0x0510:0x0511 2 m ii management control/status 0x0512 1 phy address 0x0513 1 phy register address 0x0514:0x0515 2 phy data 0x0516 1 m ii management ecat access state 0x0517 1 m ii management pd i access state 0x0518:0x051b 4 phy port status table 63: m ii management i nterface register overview 6.4.12.1 m ii management control/status ( 0x0510:0x0511 ) bit description ecat pd i reset value 0 write enable*: 0: write disabled 1: write enabled this bit is always 1 if pd i has m i control. r/(w) r/- 1 management i nterface can be controlled by pd i (registers 0x0516:0x0517 ): 0: only ecat control 1: pd i control possible r/- r/- 2 m i link detection (link con 1 guration, link detec- tion, registers 0x0518:0x051b ): 0: not available 1: m i link detection active r/- r/- 7:3 phy address of port 0 r/- r/- 9:8 command register*: write: i nitiate command. read: currently executed command commands: 00: no command/m i idle (clear error bits) 01: read 10: write others: reserved/invalid commands (do not issue) r/(w) r/(w) 12:10 reserved, write 0 r/- r/- ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 83 / 204 bit description ecat pd i reset value 13 read error: 0: no read error 1: read error occurred (phy or register not available) cleared by writing to this register. r/(w) r/(w) 14 command error: 0: last command was successful 1: i nvalid command or write command without write enable cleared with a valid command or by writing " 00" to command register bits [9:8]. r/- r/- 15 busy: 0: m i control state machine is idle 1: m i control state machine is active r/- r/- table 64: register 0x0510:0x0511 (m i cntrl/state) note r/ (w): write access depends on assignment of m i (ecat/pd i ). write access is generally blocked if management interface is busy ( 0x0510.15 =1). * write enable bit 0 is self-clearing at the sof of the next frame (or at the end of the pd i access), command bits [9:8] are self-clearing after the command is executed (busy ends). writing " 00" to the command register will also clear the error bits [14:13]. the command bits are cleared after the command is executed. 6.4.12.2 phy address ( 0x0512 ) bit description ecat pd i reset value 0:4 phy address r/(w) r/(w) 6:5 reserved, write 0 r/- r/- 7 show con 1 gured phy address of port 0-3 in register 0x0510.7:3 . select port x with bits [4:0] of this register (valid values are 0-3): 0: show address of port 0 (o ? set) 1: show individual address of port x r/(w) r/(w) table 65: register 0x0512 (phy address) note r/ (w): write access depends on assignment of m i (ecat/pd i ). write access is generally blocked if management interface is busy ( 0x0510.15 =1). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 84 / 204 6.4.12.3 phy register address ( 0x0513 ) bit description ecat pd i reset value 4:0 address of phy register that shall be read/writ- ten r/(w) r/(w) 7:5 reserved, write 0 r/(w) r/(w) table 66: register 0x0513 (phy register address) note r/ (w): write access depends on assignment of m i (ecat/pd i ). write access is generally blocked if management interface is busy ( 0x0510.15 =1). 6.4.12.4 phy data ( 0x0514:0x0515 ) bit description ecat pd i reset value 15:0 phy read/write data r/(w) r/(w) table 67: register 0x0514:0x0515 (phy data) note r/ (w): write access depends on assignment of m i (ecat/pd i ). access is generally blocked if management interface is busy ( 0x0510.15 =1). 6.4.12.5 m ii management ecat access state ( 0x0516 ) bit description ecat pd i reset value 31:0 access to m ii management: 0: ecat enables pd i takeover of m ii manage- ment control 1: ecat claims exclusive access to m ii manage- ment r/(w) r/- 31:0 reserved, write 0 r/- r/- table 68: register 0x0516 (m i ecat state) note r/ (w): write access is only possible if 0x0517.0 =0. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 85 / 204 6.4.12.6 m ii management pd i access state ( 0x0517 ) bit description ecat pd i reset value 0 access to m ii management: 0: ecat has access to m ii management 1: pd i has access to m ii management r/- r/(w) 1 force pd i access state: 0: do not change bit 0x0517.0 1: reset bit 0x0517.0 to 0 r/w r/- 7:2 reserved, write 0 r/- r/- table 69: register 0x0517 (m i pd i state) 6.4.12.7 phy port status ( 0x0518:0x051b ) bit description ecat pd i reset value 0 physical link status (phy status register 1.2): 0: no physical link / 1: physical link detected r/- r/- 1 link status (100 mbit/s, full duplex, autonego- tiation): 0: no link / 1: link detected r/- r/- 2 link status error: 0: no error 1: link error, link inhibited r/- r/- 3 read error: 0: no read error occurred 1: a read error has occurred cleared by writing any value to at least one of the phy status port registers. r/ (w/clr) r/ (w/clr) 4 link partner error: 0: no error detected / 1: link partner error r/- r/- 5 phy con 1 guration updated: 0: no update 1: phy con 1 guration was updated cleared by writing any value to at least one of the phy status port registers. r/ (w/clr) r/ (w/clr) 31:0 reserved r/- r/- table 70: register 0x0518+y (phy port status) note r/(w): write access depends on assignment of m i (ecat/pd i ). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 86 / 204 6.4.13 fmmus address length (byte) description 0x0600:0x06ff 16x16 fmmu[15:0] +0x0:0x3 4 logical start address +0x4:0x5 2 length +0x6 1 logical start bit +0x7 1 logical stop bit +0x8:0x9 2 physical start address +0xa 1 physical start bit +0xb 1 type +0xc 1 activate +0xd:0xf 3 reserved table 71: fmmu register overview for the following registers use y as fmmu number. see the device features on how many fmmus are supported in a speci 1 c esc device. 6.4.13.1 logical start address ( +0x0:0x3 ) bit description ecat pd i reset value 31:0 logical start address within the ethercat ad- dress space. r/w r/- table 72: register 0x06y0:0x06y3 (log start addr) 6.4.13.2 length ( +0x4:0x5 ) bit description ecat pd i reset value 15:0 o ? set from the 1 rst logical fmmu byte to the last fmmu byte + 1 (e.g., if two bytes are used then this parameter shall contain 2) r/w r/- table 73: register 0x06y4:0x06y5 (fmmu length) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 87 / 204 6.4.13.3 logical start bit ( +0x6 ) bit description ecat pd i reset value 2:0 logical starting bit that shall be mapped (bits are counted from least signi 1 cant bit (=0) to most signi 1 cant bit(=7) r/w r/- 7:3 reserved, write 0 r/- r/- table 74: register 0x06y6 (log. start bit) 6.4.13.4 logical stop bit ( +0x7 ) bit description ecat pd i reset value 2:0 last logical bit that shall be mapped (bits are counted from least signi 1 cant bit (=0) to most signi 1 cant bit(=7) r/w r/- 7:3 reserved, write 0 r/- r/- table 75: register 0x06y7 (log. stop bit)) 6.4.13.5 physical start address ( +0x8:0x9 ) bit description ecat pd i reset value physical start address (mapped to logical start address) r/w r/- table 76: register 0x06y8:0x06y9 (phy. start addr 6.4.13.6 physical start bit ( +0xa ) bit description ecat pd i reset value 2:0 physical starting bit as target of logical start bit mapping (bits are counted from least signi 1 - cant bit (=0) to most signi 1 cant bit(=7) r/w r/- 7:3 reserved, write 0 r/- r/- table 77: register 0x06ya (phy. start bit) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 88 / 204 6.4.13.7 type ( +0xb ) bit description ecat pd i reset value 0 0: i gnore mapping for read accesses 1: use mapping for read accesses r/w r/- 1 0: i gnore mapping for write accesses 1: use mapping for write accesses r/w r/- 7:2 reserved, write 0 r/- r/- table 78: register 0x06yb (fmmu type) 6.4.13.8 activate ( +0xc ) bit description ecat pd i reset value 0 0: fmmu deactivated 1: fmmu activated. fmmu checks logical ad- dressed blocks to be mapped according to mapping con 1 gured r/w r/- 7:1 reserved, write 0 r/- r/- table 79: register 0x06yc (fmmu activate) 6.4.13.9 reserved ( +0xd:0xf ) bit description ecat pd i reset value 23:0 reserved, write 0 r/- r/- table 80: register 0x06yd:0x06yf (reserved) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 89 / 204 6.4.14 syncmanagers address length (byte) description 0x0800:0x087f 16x8 syncmanager[15:0] +0x0:0x1 2 physical start address +0x2:0x3 2 length +0x4 1 control register +0x5 1 status register +0x6 1 activate +0x7 1 pd i control table 81: syncmanager register overview for the following registers use y as sm number. see the device features on how many sms are supported in a speci 1 c esc device. 6.4.14.1 physical start address ( +0x0:0x1 ) bit description ecat pd i reset value 15:0 speci 1 es 1 rst byte that will be handled by sync- manager r/(w) r/- table 82: register 0x0800+y*8:0x0801+y*8 (phy. start addr) note r/(w): register can only be written if syncmanager is disabled (+ 0x6.0 = 0). 6.4.14.2 length ( +0x2:0x3 ) bit description ecat pd i reset value 15:0 number of bytes assigned to syncmanager (shall be greater 1, otherwise syncmanager is not activated. i f set to 1, only watchdog trigger is generated if con 1 gured) r/(w) r/- table 83: register 0x0802+y*8:0x0803+y*8 (sm length) note r/(w): register can only be written if syncmanager is disabled ( +0x6.0 = 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 90 / 204 6.4.14.3 control register ( +0x4 ) bit description ecat pd i reset value 1:0 operation mode: 00: bu ? ered (3 bu ? er mode) 01: reserved 10: mailbox (single bu ? er mode) 11: reserved r/(w) r/- 3:2 direction: 00: read: ecat read access, pd i write access. 01: write: ecat write access, pd i read access. 10: reserved 11: reserved r/(w) r/- 4 i nterrupt in ecat event request register: 0: disabled 1: enabled r/(w) r/- 5 i nterrupt in pd i event request register: 0: disabled 1: enabled r/(w) r/- 6 watchdog trigger enable: 0: disabled 1: enabled r/w r/- 7 reserved, write 0 r/- r/- table 84: register 0x0804+y*8 (sm control) note r/(w): register can only be written if syncmanager is disabled ( +0x6.0 = 0). 6.4.14.4 status register ( +0x5 ) bit description ecat pd i reset value 0 i nterrupt write: 1: i nterrupt after bu ? er was completely and successfully written 0: i nterrupt cleared after 1 rst byte of bu ? er was read note: this interrupt is signaled to the reading side if enabled in the sm control register. r/- r/- 1 i nterrupt read: 1: i nterrupt after bu ? er was completely and successful read 0: i nterrupt cleared after 1 rst byte of bu ? er was written note: this interrupt is signaled to the writing side if enabled in the sm control register. r/- r/- ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 91 / 204 bit description ecat pd i reset value 2 reserved r/- r/- 3 mailbox mode: mailbox status: 0: mailbox empty 1: mailbox full bu ? ered mode: reserved r/- r/- 5:4 bu ? ered mode: bu ? er status (last written bu ? er): 00: 1. bu ? er 01: 2. bu ? er 10: 3. bu ? er 11: (no bu ? er written) mailbox mode: reserved r/- r/- 6 read bu ? er in use (opened) r/- r/- 7 write bu ? er in use (opened) r/- r/- table 85: register 0x0805+y*8 (sm status) 6.4.14.5 activate ( +0x6 ) bit description ecat pd i reset value 0 syncmanager enable/disable: 0: disable: access to memory without sync- manager control 1: enable: syncmanager is active and controls memory area set in con 1 guration r/w r/ (w ack)* 1 repeat request: a toggle of repeat request means that a mail- box retry is needed (primarily used in conjunc- tion with ecat read mailbox) r/w r/- 5:2 reserved, write 0 r/- r/ (w ack)* 6 latch event ecat: 0: no 1: generate latch event if ethercat master issues a bu ? er exchange r/w r/ (w ack)* 7 latch event pd i : 0: no 1: generate latch events if pd i issues a bu ? er exchange or if pd i ac- cesses bu ? er start address r/w r/ (w ack)* table 86: register 0x0806+y*8 (sm activate) * pd i register function acknowledge by write command is disabled: reading this register from pd i in all sms which have changed activation clears al event request 0x0220.4 . writing to this register from pd i is ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 92 / 204 not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i in all sms which have changed activation clears al event request 0x0220.4 . writing to this register from pd i is possible; write value is ignored (write 0). 6.4.14.6 pd i control ( +0x7 ) bit description ecat pd i reset value 0 deactivate syncmanager: read: 0: normal operation, syncmanager activated. 1: syncmanager deactivated and reset sync- manager locks access to memory area. write: 0: activate syncmanager 1: request syncmanager deactivation note: writing 1 is delayed until the end of a frame which is currently processed. r/- r/w 1 repeat ack: i f this is set to the same value as set by repeat request, the pd i acknowledges the execution of a previous set repeat request. r/- r/w 7:2 reserved, write 0 r/- r/- table 87: register 0x0807+y*8 (sm pd i control) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 93 / 204 6.4.15 distributed clocks receive times depending on the available width of the distributed clocks feature the time stamp registers are either 32 bit (4 bytes) or 64 bits (8 bytes) wide. please check the feature summary of the respective tr i nam i c esc device. 6.4.15.1 receive time port 0 ( 0x0900:0x0903 ) bit description ecat pd i reset value 31:0 write: a write access to register 0x0900 with bwr or fpwr latches the local time of the beginning of the receive frame (start 1 rst bit of preamble) at each port. read: local time of the beginning of the last receive frame containing a write access to this register. r/w (special func- tion) r/- table 88: register 0x0900:0x0903 (rcv time p0) note the time stamps cannot be read in the same frame in which this register was written. 6.4.15.2 receive time port 1 ( 0x0904:0x0907 ) bit description ecat pd i reset value 31:0 local time of the beginning of a frame (start 1 rst bit of preamble) received at port 1 contain- ing a bwr or fpwr to register 0x0900 . r/- r/- table 89: register 0x0904:0x0907 (rcv time p1) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 94 / 204 6.4.16 distributed clocks time loop control unit time loop control unit is usually assigned to ecat. write access to time loop control registers by pd i (and not ecat) depends on explicit hardware con 1 guration and on the used esc type. check the device features for availability. 6.4.16.1 system time ( 0x0910:0x0917 ) bit description ecat pd i reset value 0:63 ecat read access: local copy of system time when frame passed the reference clock (i.e., including system time delay). time latched at beginning of the frame (ethernet sof delimiter) r - 63:0 pd i read access: local copy of the system time. time latched when reading 1 rst byte ( 0x0910 ) - r 31:0 write access: written value will be compared with the local copy of the system time. the result is an input to the time control loop. note: written value will be compared at the end of the frame with the latched (sof) local copy of the system time if at least the 1 rst byte ( 0x0910 ) was written. (w) (spe- cial func- tion) r/- 31:0 write access: written value will be compared with latch0 time positive edge time. the result is an input to the time control loop. note: written value will be compared at the end of the access with latch0 time positive edge ( 0x09b0:0x09b3 ) if at least the last byte ( 0x0913 ) was written. - (w) (spe- cial func- tion) table 90: register 0x0910:0x0917 (system time) note write access to this register depends upon esc con 1 guration (typically ecat, pd i only with explicit esc con 1 guration: system time pd i controlled). 6.4.16.2 receive time ecat processing unit ( 0x0918:0x091f ) bit description ecat pd i reset value 63:0 local time of the beginning of a frame (start 1 rst bit of preamble) received at the ecat pro- cessing unit containing a write access to regis- ter 0x0900 note: e.g., if port 0 is open, this register re 2 ects the receive time port 0 as a 64 bit value. r/- r/- table 91: register 0x0918:0x091f (rcv time epu) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 95 / 204 6.4.16.3 system time o ? set ( 0x0920:0x0927 ) bit description ecat pd i reset value 63:0 di ? erence between local time and system time. o ? set is added to the local time. r/(w) r/(w) table 92: register 0x0920:0x0927 (sys time o ? set) note write access to this register depends upon esc con 1 guration (typically ecat, pd i only with explicit esc con 1 guration: system time pd i controlled). reset internal system time di ? erence 1 lter and speed counter 1 lter by writing speed counter start ( 0x0930:0x0931 ) after changing this value. 6.4.16.4 system time delay ( 0x0928:0x092b ) bit description ecat pd i reset value 31:0 delay between reference clock and the esc r/(w) r/(w) table 93: register 0x0928:0x092b (sys time delay) note write access to this register depends upon esc con 1 guration (typically ecat, pd i only with explicit esc con 1 guration: system time pd i controlled). reset internal system time di ? erence 1 lter and speed counter 1 lter by writing speed counter start ( 0x0930:0x0931 ) after changing this value. 6.4.16.5 system time di ? erence ( 0x092c:0x092f ) bit description ecat pd i reset value 30:0 mean di ? erence between local copy of system time and received system time values r/- r/- 31 0: local copy of system time greater than or equal received system time 1: local copy of system time smaller than re- ceived system time r/- r/- table 94: register 0x092c:0x092f (sys time di ? ) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 96 / 204 6.4.16.6 speed counter start ( 0x0930:0x0931 ) bit description ecat pd i reset value 14:0 bandwidth for adjustment of local copy of sys- tem time (larger values ! smaller bandwidth and smoother adjustment) a write access resets system time di ? er- ence ( 0x092c:0x092f ) and speed counter di ? ( 0x0932:0x0933 ). minimum value: 0x0080 to 0x3fff r/(w) r/(w) 15 reserved, write 0 r/(w) r/- table 95: register 0x0930:0x931 (speed cnt start) note write access to this register depends upon esc con 1 guration (typically ecat, pd i only with explicit esc con 1 guration: system time pd i controlled). 6.4.16.7 speed counter di ? ( 0x0932:0x0933 ) bit description ecat pd i reset value 15:0 representation of the deviation between local clock period and reference clock s clock period (representation: two s complement) range: (speed counter start - 0x7f ) r/- r/- table 96: register 0x0932:0x0933 (speed cnt di ? ) note calculate the clock deviation after system time di ? erence has settled at a low value as follows: deviation = speedcntdif f 5 ( speedcntstart + speedcntdif f +2) ( speedcntstart speedcntdif f +2) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 97 / 204 6.4.16.8 system time di ? erence filter depth ( 0x0934 ) bit description ecat pd i reset value 3:0 filter depth for averaging the received system time deviation. a write access resets system time di ? erence ( 0x092c:0x092f ) r/(w) r/(w) 7:4 reserved, write 0 r/- r/- table 97: register 0x0934 (sys time di ? filter) note write access to this register depends upon esc con 1 guration (typically ecat, pd i only with explicit esc con 1 guration: system time pd i controlled). 6.4.16.9 speed counter filter depth ( 0x0935 ) bit description ecat pd i reset value 3:0 filter depth for averaging the clock period devi- ation. a write access resets the internal speed counter 1 lter. r/(w) r/(w) 7:4 reserved, write 0 r/- r/- table 98: register 0x0935 (speed cnt filter depth) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 98 / 204 6.4.17 distributed clocks cyclic unit control 6.4.17.1 cyclic unit control ( 0x0980 ) bit description ecat pd i reset value 0 sync out unit control: 0: ecat controlled 1: pd i controlled r/w r/- 3:1 reserved, write 0 r/- r/- 4 latch i n unit 0: 0: ecat controlled 1: pd i controlled note: always 1 (pd i controlled) if system time is pd i controlled. latch interrupt is routed to ecat/pd i depending on this setting r/w r/- 5 latch i n unit 1: 0: ecat controlled 1: pd i controlled note: latch interrupt is routed to ecat/pd i depending on this setting r/w r/- 7:6 reserved, write 0 r/- r/- table 99: register 0x0980 (cyclic unit cntrl) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 99 / 204 6.4.18 distributed clocks sync out unit 6.4.18.1 sync out activation ( 0x0981 ) bit description ecat pd i reset value 0 sync out unit activation: 0: deactivated 1: activated r/(w) r/(w) 0 1 sync0 generation: 0: deactivated 1: sync0 pulse is generated r/(w) r/(w) 0 2 sync1 generation: 0: deactivated 1: sync1 pulse is generated r/(w) r/(w) 0 3 auto-activation by writing start time cyclic op- eration (0x0990:0x0997): 0: disabled 1: auto-activation enabled. 0x0981.0 is set au- tomatically after start time is written. r/(w) r/(w) 0 4 extension of start time cyclic operation ( 0x0990:0x0993 ): 0: no extension 1: extend 32 bit written start time to 64 bit r/(w) r/(w) 0 5 start time plausibility check: 0: disabled. syncsignal generation if start time is reached. 1: i mmediate syncsignal generation if start time is outside near future (see 0x0981.6 ) r/(w) r/(w) 0 6 near future con 1 guration (approx.): 0: 1 = 2 dc width future ( 2 31 ns or 2 63 ns) 1: 2.1 sec. future ( 2 31 ns) r/(w) r/(w) 0 7 syncsignal debug pulse (vasily bit): 0: deactivated 1: i mmediately generate one ping only on sync0-1 according to 0x0981.(2:1) for debug- ging this bit is self-clearing, always read 0. r/(w) r/(w) 0 table 100: register 0x0981 (sync out activation) note write to this register depends upon setting of 0x0980.0 . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 100 / 204 6.4.18.2 pulse length of sync signals ( 0x0982:0x0983 ) bit description ecat pd i reset value 0 pulse length of syncsignals (in units of 10ns) 0: acknowledge mode: syncsignal will be cleared by reading sync[1:0] status register r/- r/- 0, later eeprom adr 0x0002 table 101: register 0x0982:0x0983 (sync pulse length) 6.4.18.3 activation status ( 0x0984 ) bit description ecat pd i reset value 0 sync0 activation state: 0: first sync0 pulse is not pending 1: first sync0 pulse is pending r/- r/- 0 1 sync1 activation state: 0: first sync1 pulse is not pending 1: first sync1 pulse is pending r/- r/- 0 2 start time cyclic operation ( 0x0990:0x0997 ) plausibility check result when sync out unit was activated: 0: start time was within near future 1: start time was out of near future ( 0x0981.6 ) r/- r/- 0 7:3 reserved r/- r/- 0 table 102: register 0x0984 (activation status) 6.4.18.4 sync0 status ( 0x098e ) bit description ecat pd i reset value 0 sync0 activation state: 0: first sync0 pulse is not pending 1: first sync0 pulse is pending r/- r/ (w ack)* 0 7:1 reserved r/- r/ (w ack)* 0 table 103: register 0x098e (sync0 status) * pd i register function acknowledge by write command is disabled: reading this register from pd i clears al event request 0x0220.2 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i clears al event request 0x0220.2 . writing to this register from pd i is possible; write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 101 / 204 6.4.18.5 sync1 status ( 0x098f ) bit description ecat pd i reset value 0 sync1 activation state: 0: first sync1 pulse is not pending 1: first sync1 pulse is pending r/- r/ (w ack)* 0 7:1 reserved r/- r/ (w ack)* 0 table 104: register 0x098f (sync1 status) * pd i register function acknowledge by write command is disabled: reading this register from pd i clears al event request 0x0220.3 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i clears al event request 0x0220.3 . writing to this register from pd i is possible; write value is ignored (write 0). 6.4.18.6 start time cyclic operation / next sync0 pulse ( 0x0990:0x0997 ) bit description ecat pd i reset value 63:0 write: start time (system time) of cyclic opera- tion in ns read: system time of next sync0 pulse in ns r/(w) r/(w) 0 table 105: register 0x0990:0x0997 (start time cyclic operation) note write to this register depends upon setting of 0x0980.0 . only writable if 0x0981.0 =0. auto-activation ( 0x0981.3 =1): upper 32 bits are automatically ex- tended if only lower 32 bits are written within one frame. 6.4.18.7 next sync1 pulse ( 0x0998:0x099f ) bit description ecat pd i reset value 63:0 system time of next sync1 pulse in ns r/- r/- 0 table 106: register 0x0998:0x099f (next sync1) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 102 / 204 6.4.18.8 sync0 cycle time ( 0x09a0:0x09a3 ) bit description ecat pd i reset value 31:0 wtime between two consecutive sync0 pulses in ns. 0: single shot mode, generate only one sync0 pulse. r/(w) r/(w) 0 table 107: register 0x09a0:0x09a3 (sync0 cycle time) note write to this register depends upon setting of 0x0980.0 . 6.4.18.9 sync1 cycle time ( 0x09a4:0x09a7 ) bit description ecat pd i reset value 31:0 time between sync1 pulses and sync0 pulse in ns r/(w) r/(w) 0 table 108: register 0x09a4:0x09a7 (sync1 cycle time) note write to this register depends upon setting of 0x0980.0 . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 103 / 204 6.4.19 distributed clocks latch i n unit 6.4.19.1 latch0 control ( 0x09a8 ) bit description ecat pd i reset value 0 latch0 positive edge: 0: continuous latch active 1: single event (only 1 rst event active) r/(w) r/(w) 0 1 latch0 negative edge: 0: continuous latch active 1: single event (only 1 rst event active) r/(w) r/(w) 0 7:2 reserved, write 0 r/- r/- 0 table 109: register 0x09a8 (latch0 control) note write access depends upon setting of 0x0980.4 . 6.4.19.2 latch1 control ( 0x09a9 ) bit description ecat pd i reset value 0 latch1 positive edge: 0: continuous latch active 1: single event (only 1 rst event active) r/(w) r/(w) 0 1 latch01 negative edge: 0: continuous latch active 1: single event (only 1 rst event active) r/(w) r/(w) 0 7:2 reserved, write 0 r/- r/- 0 table 110: register 0x09a9 (latch1 control) note write access depends upon setting of 0x0980.5 . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 104 / 204 6.4.19.3 latch0 status ( 0x09ae ) bit description ecat pd i reset value 0 event latch0 positive edge. 0: positive edge not detected or continuous mode 1: positive edge detected in single event mode only. flag cleared by reading out latch0 time posi- tive edge. r/- r/- 0 1 event latch0 negative edge. 0: negative edge not detected or continuous mode 1: negative edge detected in single event mode only. flag cleared by reading out latch0 time nega- tive edge. r/- r/- 0 2 latch0 pin state r/- r/- 0 7:3 reserved r/- r/- 0 table 111: register 0x09ae (latch0 status) 6.4.19.4 latch1 status ( 0x09af ) bit description ecat pd i reset value 0 event latch1 positive edge. 0: positive edge not detected or continuous mode 1: positive edge detected in single event mode only. flag cleared by reading out latch1 time posi- tive edge. r/- r/- 0 1 event latch1 negative edge. 0: negative edge not detected or continuous mode 1: negative edge detected in single event mode only. flag cleared by reading out latch1 time nega- tive edge. r/- r/- 0 2 latch1 pin state r/- r/- 0 7:3 reserved r/- r/- 0 table 112: register 0x09af (latch1 status) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 105 / 204 6.4.19.5 latch0 time positive edge ( 0x09b0:0x09b7 ) bit description ecat pd i reset value 63:0 register captures system time at the positive edge of the latch0 signal. r(ack)/- r/ (w ack)* 0 table 113: register 0x09b0:0x09b7 (latch0 time pos edge) note register bits [63:8] are internally latched (ecat/pd i independently) when bits [7:0] are read, which guarantees reading a consistent value. reading this register from ecat clears latch0 status 0x09ae.0 if 0x0980.4 =0. writing to this register from ecat is not possible. * pd i register function acknowledge by write command is disabled: reading this register from pd i if 0x0980.4 =1 clears latch0 status 0x09ae.0 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i if 0x0980.4 =1 clears latch0 status 0x09ae.0 . writing to this register from pd i is possible; write value is ignored (write 0). 6.4.19.6 latch0 time negative edge ( 0x09b8:0x09bf ) bit description ecat pd i reset value 63:0 register captures system time at the negative edge of the latch0 signal. r(ack)/- r/ (w ack)* 0 table 114: register 0x09b8:0x09bf (latch0 time neg edge) note register bits [63:8] are internally latched (ecat/pd i independently) when bits [7:0] are read, which guarantees reading a consistent value. reading this register from ecat clears latch0 status 0x09ae.1 if 0x0980.4 =0. writing to this register from ecat is not possible. * pd i register function acknowledge by write command is disabled: reading this register from pd i if 0x0980.4 =1 clears latch0 status 0x09ae.1 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i if 0x0980.4 =1 clears latch0 status 0x09ae.1 . writing to this register from pd i is possible; write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 106 / 204 6.4.19.7 latch1 time positive edge ( 0x09c0:0x09c7 ) bit description ecat pd i reset value 63:0 register captures system time at the positive edge of the latch1 signal. r(ack)/- r/ (w ack)* 0 table 115: register 0x09c0:0x09c7 (latch1 time pos edge) note register bits [63:8] are internally latched (ecat/pd i independently) when bits [7:0] are read, which guarantees reading a consistent value. reading this register from ecat clears latch1 status 0x09af.0 if 0x0980.5 =0. writing to this register from ecat is not possible. * pd i register function acknowledge by write command is disabled: reading this register from pd i if 0x0980.5 =1 clears latch1 status 0x09af.0 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i if 0x0980.5 =1 clears latch1 status 0x09af.0 . writing to this register from pd i is possible; write value is ignored (write 0). 6.4.19.8 latch1 time negative edge ( 0x09c8:0x09cf ) bit description ecat pd i reset value 63:0 register captures system time at the negative edge of the latch1 signal. r(ack)/- r/ (w ack)* 0 table 116: register 0x09c8:0x09cf (latch1 time neg edge) note register bits [63:8] are internally latched (ecat/pd i independently) when bits [7:0] are read, which guarantees reading a consistent value. reading this register from ecat clears latch1 status 0x09af.0 if 0x0980.5 =0. writing to this register from ecat is not possible. * pd i register function acknowledge by write command is disabled: reading this register from pd i if 0x0980.5 =1 clears latch1 status 0x09af.1 . writing to this register from pd i is not possible. pd i register function acknowledge by write command is enabled: writing this register from pd i if 0x0980.5 =1 clears latch1 status 0x09af.1 . writing to this register from pd i is possible; write value is ignored (write 0). ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 107 / 204 6.4.20 distributed clocks syncmanager event times 6.4.20.1 ethercat bu ? er change event time ( 0x09f0:0x09f3 ) bit description ecat pd i reset value 31:0 register captures local time of the beginning of the frame which causes at least one sm to assert an ecat event r/- r/- 0 table 117: register 0x09f0:0x09f3 (ecat bu ? er change event time) note register bits [31:8] are internally latched (ecat/pd i independently) when bits [7:0] are read, which guarantees reading a consistent value. 6.4.20.2 pd i bu ? er start event time ( 0x09f8:0x09fb ) bit description ecat pd i reset value 31:0 register captures local time when at least one syncmanager asserts an pd i bu ? er start event r/- r/- 0 table 118: register 0x09f8:0x09fb (pd i bu ? er start event time) note register bits [31:8] are internally latched (ecat/pd i independently) when bits [7:0] are read, which guarantees reading a consistent value. 6.4.20.3 pd i bu ? er change event time ( 0x09fc:0x09ff ) bit description ecat pd i reset value 31:0 register captures local time when at least one syncmanager asserts an pd i bu ? er start event r/- r/- 0 table 119: register 0x09fc:0x09ff (pd i bu ? er change event time) note register bits [31:8] are internally latched (ecat/pd i independently) when bits [7:0] are read, which guarantees reading a consistent value. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 108 / 204 6.4.21 esc speci 1 c 6.4.21.1 product i d ( 0x0e00:0x0e07 ) bit description ecat pd i reset value 63:0 product i d r/- r/- tmc8460: 0x0000000001008460 tmc8461: 0x0000000001108461 tmc8462: 0x0000000001108461 tmc8670: 0x0000000001008670 table 120: register 0x0e00:0x0e07 (product i d) 6.4.21.2 vendor i d ( 0x0e08:0x0e0f ) bit description ecat pd i reset value 63:0 vendor i d: [23:0] company [31:24] department note: test vendor i ds [31:28]= 0xe r/- r/- tmc8460: 0x0000000100000286 tmc8461: 0x0000000100000286 tmc8462: 0x0000000100000286 tmc8670: 0x0000000100000286 table 121: register 0x0e08:0x0e0f (vendor i d) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 109 / 204 6.4.22 process data ram 6.4.22.1 process data ram ( 0x1000:0xffff ) the process data ram starts at address 0x1000 . the size of the process data ram depends on the device. bytes description ecat pd i reset value - - - process data ram (r/w) (r/w) random/unde 1 ned table 122: process data ram (0x1000:0xffff) note (r/w): process data ram is only accessible if eeprom was correctly loaded (register 0x0110.0 = 1). device process data ram size upper ram address tmc8460 16kbytes 0x4fff tmc8461 16kbytes 0x4fff tmc8462 16kbytes 0x4fff tmc8670 16kbytes 0x4fff table 123: process data ram size ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 110 / 204 7 mfc i o block description 7.1 general i nformation the mfc i o block includes a set of functions realized as dedicated hardware blocks. the mfc i o block o ? ers 24 fully con 1 gurable i os that can be used with any function of the mfc i o block. 16 low voltage i os capable of 3.3v or 5v and 8 high voltage i os capable of up to 24v are available. the mfc i o block functions can be used either via the mfc i o control interface (see section 5.2 ) or via ethercat data objects mapped as registers to the process data memory. when using the mfc i o control interface the microcontroller has full control over the mfc i o block and its hardware functions. this allows for o [ oading some 1 rmware tasks towards the tmc8462, to do system level control, or to extend the microcontroller s i o capabilities. when accessing the mfc i o block via ethercat data objects, centralized control from the ethercat master is enabled. i t it also possible to use the tmc8462 in device emulation mode without any microcontroller connected while still using the dedicated hardware blocks and functions of the mfc i o block. for example, the sp i master interface of the mfc i o block can be used to connected to a position sensor, which is read out by the ethercat master. con 1 guration of the mfc i o block is done via the s ii eeprom at startup or by the ethercat master or microcontroller after startup. s ii eeprom con 1 guration data must be of category 1 and is automatically loaded at startup and written into the esc parameter ram section of the ethercat register set starting at address 0x0580 (see section 6.4.11.1 ). the esc parameter ram section can also be written by the ethercat master or the local microcontroller for direct con 1 guration or to modify con 1 guration after startup. the block diagram in figure 31 shows the general approach for the mfc i o block con 1 guration. note even if the mfc i o block is only accessed from the microcontroller and the ethercat access feature is not used, it is recommended to store at least the crossbar con 1 guration (section 7.5 ), the hv i o con 1 guration (section 7.6 ) and the switching regulator con 1 guration (section 7.7 ) in the s ii eeprom. by doing this, the settings are loaded faster than having to write them from the microcontroller and it also reduces the memory usage on the microcontroller itself. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 111 / 204 figure 31: mfc i o block con 1 guration using the esc parameter ram ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 112 / 204 7.2 mfc i o register overview the mfc i o block contains a range of registers dedicated to the speci 1 c sub-blocks. the registers can always be read by a microcontroller via the mfc i o control sp i i nterface. the registers can only be exclusively written by either the microcontroller via the mfc i o control sp i i nterface or by the ethercat master via a mapping in the esc s dpram. the analog and high voltage block can also be con 1 gured using dedicated registers of the mfc i o block. register function write/read size (byte) padding bytes (see section 7.8 ) 0 enc_mode w 2 2 1 enc_status r 1 3 2 x_enc w 4 0 3 x_enc r 4 0 4 enc_const w 4 0 5 enc_latch r 4 0 6 sp i _rx_data r 8 0 7 sp i _tx_data w 8 0 8 sp i _conf w 2 2 9 sp i _status r 1 3 10 sp i _length w 1 3 11 sp i _t i me w 1 3 12 i 2c_t i mebase w 1 3 13 i 2c_control w 1 3 14 i 2c_status r 1 3 15 i 2c_address w 1 3 16 i 2c_data_r r 1 3 17 i 2c_data_w w 1 3 18 sd_ch0_steprate w 4 0 19 sd_ch1_steprate w 4 0 20 sd_ch2_steprate w 4 0 21 sd_ch0_stepcount r 4 0 22 sd_ch1_stepcount r 4 0 23 sd_ch2_stepcount r 4 0 24 sd_ch0_steptarget w 4 0 25 sd_ch1_steptarget w 4 0 26 sd_ch2_steptarget w 4 0 27 sd_ch0_compare w 4 0 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 113 / 204 register function write/read size (byte) padding bytes (see section 7.8 ) 28 sd_ch1_compare w 4 0 29 sd_ch2_compare w 4 0 30 sd_ch0_nextsr w 4 0 31 sd_ch1_nextsr w 4 0 32 sd_ch2_nextsr w 4 0 33 sd_steplength w 6 2 34 sd_delay w 6 2 35 sd_cfg w 3 1 36 pwm_cfg w 8 0 37 pwm1 w 2 2 38 pwm2 w 2 2 39 pwm3 w 2 2 40 pwm4 w 2 2 41 pwm1_cntrshft w 2 2 42 pwm2_cntrshft w 2 2 43 pwm3_cntrshft w 2 2 44 pwm4_cntrshft w 2 2 45 pwm_pulse_b_pulse_a w 4 0 46 pwm_pulse_length w 1 3 47 gpo w 4 0 48 gp i r 2 2 49 gp i o_conf i g w 2 2 50 dac_val w 2 2 51 mfc i o_ i rq_cfg w 3 1 52 mfc i o_ i rq_flags r 3 1 53 wd_t i me w 4 0 54 wd_cfg w 1 3 55 wd_out_mask_pol w 8 0 56 wd_oe_pol w 4 0 57 wd_ i n_mask_pol w 8 0 58 wd_max r 4 0 59 hv_ana_status r 4 0 60 unused/reserved - 0 0 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 114 / 204 register function write/read size (byte) padding bytes (see section 7.8 ) 61 unused/reserved - 0 0 62 unused/reserved - 0 0 63 sync1_sync0_event_cnt r (ecat only) 4 0 64 hv i o_cfg w 4 0 65 buck_conv_cfg w 2 2 66 al_overr i de w 1 3 table 124: mfc i o register overview for tmc8462-ba ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 115 / 204 7.3 mfc i o register set 7.3.1 i ncremental encoder i nterface 7.3.1.1 register 0 C enc_mode bit description ecat pd i range [unit] 0 pol_a required a polarity for an n channel event (0: neg., 1: pos.) r/w r/w 1 pol_b required b polarity for an n channel event (0: neg., 1: pos.) r/w r/w 2 pol_n de 1 nes active polarity of n (0: neg., 1: pos.) r/w r/w 3 ignore_ab 0: an n event occurs only when polarities given by pol_n, pol_a and pol_b match. 1: i gnore a and b polarity for n channel event r/w r/w 4 clr_cont 1: always latch or latch and clear x_enc upon an n event (once per revolution, it is recommended to combine this setting with edge sensitive n event) r/w r/w 5 clr_once 1: latch or latch and clear x_enc on the next n event fol- lowing the write access r/w r/w 7:6 neg_edge bit n & pos_edge bit p n p : n channel event sensitivity 0 0 : n channel event is active during an active n event level 0 1 : n channel is valid upon active going n event 1 0 : n channel is valid upon inactive going n event 1 1 : n channel is valid upon active going and inactive going n event r/w r/w 8 clr_enc_x 0: on n event, x_enc becomes latched to enc_latch only 1: latch & additionally clear x_enc at n-event r/w r/w 9 latch_x_act 1: also latch xactual position together with x_enc. allows latching the ramp generator position upon an n channel event as selected by pos_edge and neg_edge. r/w r/w 10 enc_sel_decimal 0: encoder prescaler divisor binary mode: counts enc_const(fractional part) / 65536 1: encoder prescaler divisor decimal mode: counts in enc_const(fractional part) / 10000 r/w r/w 15:11 reserved -/- -/- table 125: mfc i o register 0 C enc_mode ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 116 / 204 7.3.1.2 register 1 C enc_status bit description ecat pd i range [unit] 0 n_event 1: encoder n event detected. status bit is cleared on read: read (r) + clear (c) this event can also be ored into the interrupt output signal. see register 51 and 52 . r+c/- r+c/- 7:1 reserved r/- r/- table 126: mfc i o register 1 C enc_status 7.3.1.3 register 2 C x_enc (write) bit description ecat pd i range [unit] 31:0 actual encoder position (signed) r/w r/w 2 31 . . . +(2 31 ) 1 table 127: mfc i o register 2 C x_enc (write) 7.3.1.4 register 3 C x_enc (read) bit description ecat pd i range [unit] 31:0 actual encoder position (signed) r/- r/- 2 31 . . . +(2 31 ) 1 table 128: mfc i o register 3 C x_enc (read) 7.3.1.5 register 4 C enc_const bit description ecat pd i range [unit] 31:0 accumulation constant (signed) 16 bit integer part, 16 bit fractional part x_enc accumulates en c _ con st (2 16 x _ en c ) (binary) or en c _ con st (10 4 x _ en c ) (decimal) enc_mode bit enc_sel_decimal switches be- tween decimal and binary setting. use the sign, to match rotation direction! r/w r/w binary: [ steps= 2 16 ] (0 : : : 32767 : 9999847) decimal: (0 : : : 32767 : 9999) reset default = 1 : 0(= 65536) table 129: mfc i o register 4 C enc_const ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 117 / 204 7.3.1.6 register 5 C enc_latch bit description ecat pd i range [unit] 31:0 encoder position x_enc latched on n event r/- r/- 2 31 . . . +(2 31 ) 1 table 130: mfc i o register 5 C enc_latch ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 118 / 204 7.3.2 sp i master i nterface 7.3.2.1 register 6 C sp i _rx_data bit description ecat pd i range [unit] 63:0 received data from last sp i transfer for sp i transfers with less than 64 bit, the upper bits of this register are unused r/- r/- table 131: mfc i o register 6 C sp i _rx_data 7.3.2.2 register 7 C sp i _tx_data bit description ecat pd i range [unit] 63:0 data to transmit on next sp i transfer for sp i transfers with less than 64 bit, the upper bits of this register are unused -/w -/w table 132: mfc i o register 7 C sp i _tx_data note unless con 1 gured otherwise in the sp i _conf register (bits 10:8), writing data into this register automatically starts transmission as soon as the highest byte (according to sp i _length con 1 guration) has been written. all bytes to be transmitted must be written to the register within a single access (via mfc i o control sp i or from the dpram) to ensure data consistency. 7.3.2.3 register 8 C sp i _conf bit description ecat pd i range [unit] 1:0 selection of sp i slave r/w r/w 2 reserved r/w r/w 3 keep cs low after transfer for transfers greater than 64bit r/w r/w 4 transmit lsb 1 rst r/w r/w 5 sp i clock phase r/w r/w 6 sp i clock polarity r/w r/w 7 reserved r/w r/w ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 119 / 204 bit description ecat pd i range [unit] 10:8 trigger con 1 guration for transmission start 000 2 : start when data is written into tx register 001 2 : start on beginning of pwm cycle 010 2 : start on center of pwm cycle 011 2 : start on pwm a mark 100 2 : start on pwm b mark 101 2 : start on pwm a&b marks 110 2 : reserved 111 2 : start on single trigger (bit 15) r/w r/w 0 10 : : : 7 10 14:11 reserved r/w r/w 15 start transfer once when this bit is set and trig- ger con 1 guration is set to 111 2 r/w r/w table 133: mfc i o register 8 C sp i _conf 7.3.2.4 register 9 C sp i _status bit description ecat pd i range [unit] 0 sp i transfer done, ready for next transfer r/- r/- 7:1 unused r/- r/- 0 table 134: mfc i o register 9 C sp i _status 7.3.2.5 register 10 C sp i _length bit description ecat pd i range [unit] 5:0 sp i datagram length example: 000111 2 = 8 bit datagram example: 111111 2 = 64 bit datagram -/w -/w 0 10 : : : 63 10 [bit] 7:6 unused -/w -/w 0 table 135: mfc i o register 10 C sp i _length 7.3.2.6 register 11 C sp i _t i me bit description ecat pd i range [unit] 7:0 sp i _b i t_durat i on f sp i = 25 m hz (4+(2 sp i _ bit _ du rat ion )) -/w -/w 0 10 : : : 255 10 table 136: mfc i o register 11 C sp i _t i me ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 120 / 204 7.3.3 i 2c master i nterface 7.3.3.1 register 12 C i 2c_t i mebase bit description ecat pd i range [unit] 7:0 i 2c_b i t_durat i on 0 = o ? 1 : : : 255 = 1 s : : : 255 s = 250 kbit=s : : : 980 bit=s -/w -/w 0 10 : : : 255 10 [ s ] table 137: mfc i o register 12 C i 2c_t i mebase 7.3.3.2 register 13 C i 2c_control bit description ecat pd i range [unit] 0 receive data and send nack -/w -/w 1 receive data and send ack -/w -/w 2 send data (content of data i 2c_data_w) -/w -/w 3 send address (content of address register i 2c_address), incl. r/nw bit -/w -/w 4 send stop condition -/w -/w 5 send start condition (also repeated start) -/w -/w 7:6 unused -/w -/w table 138: mfc i o register 13 C i 2c_control 7.3.3.3 register 14 C i 2c_status bit description ecat pd i range [unit] 0 st - start condition sent r/- r/- 1 rst - repeated start condition sent r/- r/- 2 adr - transmit address mode r/- r/- 3 rx - read from slave mode r/- r/- 4 tx - write to slave mode r/- r/- 5 ack - acknowledge received/sent r/- r/- 6 nak - not acknowledge received/sent r/- r/- 7 err - error flag r/- r/- table 139: mfc i o register 14 C i 2c_status ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 121 / 204 7.3.3.4 register 15 C i 2c_address bit description ecat pd i range [unit] 0 r/nw bit -/w -/w 7:1 address -/w -/w table 140: mfc i o register 15 C i 2c_address 7.3.3.5 register 16 C i 2c_data_r bit description ecat pd i range [unit] 7:0 received data r/- r/- table 141: mfc i o register 16 C i 2c_data_r 7.3.3.6 register 17 C i 2c_data_w bit description ecat pd i range [unit] 7:0 transmit data -/w -/w table 142: mfc i o register 17 C i 2c_data_w ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 122 / 204 7.3.4 step and direction signal generator 7.3.4.1 register 18 C sd_ch0_steprate bit description ecat pd i range [unit] 31:0 signed accumulation constant c for sd_ch0. this accumulation constant determines the time tstep between two successive steps and thereby the step frequency. the sign (msb) of this accumulation constant is used for the direction signal output (d0, d0n). the accumulation constant c is 2th comple- ment. (see also section 7.14 ) -/w -/w 0 . . . +(2 32 ) 1 table 143: mfc i o register 18 C sd_ch0_steprate 7.3.4.2 register 19 C sd_ch1_steprate bit description ecat pd i range [unit] 31:0 signed accumulation constant c for sd_ch1. this accumulation constant determines the time tstep between two successive steps and thereby the step frequency. the sign (msb) of this accumulation constant is used for the direction signal output (d1, d1n). the accumulation constant c is 2th comple- ment. (see also section 7.14 ) -/w -/w 0 . . . +(2 32 ) 1 table 144: mfc i o register 19 C sd_ch1_steprate 7.3.4.3 register 20 C sd_ch2_steprate bit description ecat pd i range [unit] 31:0 signed accumulation constant c for sd_ch2. this accumulation constant determines the time tstep between two successive steps and thereby the step frequency. the sign (msb) of this accumulation constant is used for the direction signal output (d2, d2n). the accumulation constant c is 2th comple- ment. (see also section 7.14 ) -/w -/w 0 . . . +(2 32 ) 1 table 145: mfc i o register 20 C sd_ch2_steprate ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 123 / 204 7.3.4.4 register 21 C sd_ch0_stepcount bit description ecat pd i range [unit] 31:0 step counter for sd_ch0. counting up/down depending on step direc- tion. r/- r/- 2 31 . . . +(2 31 ) 1 table 146: mfc i o register 21 C sd_ch0_stepcount 7.3.4.5 register 22 C sd_ch1_stepcount bit description ecat pd i range [unit] 31:0 step counter for sd_ch1. counting up/down depending on step direc- tion. r/- r/- 2 31 . . . +(2 31 ) 1 table 147: mfc i o register 22 C sd_ch1_stepcount 7.3.4.6 register 23 C sd_ch2_stepcount bit description ecat pd i range [unit] 31:0 step counter for sd_ch2. counting up/down depending on step direc- tion. r/- r/- 2 31 . . . +(2 31 ) 1 table 148: mfc i o register 23 C sd_ch2_stepcount 7.3.4.7 register 24 C sd_ch0_steptarget bit description ecat pd i range [unit] 31:0 steps pulses (= distance) to be made for sd_ch0. can be overwritten at any time. when zero, no more step pulses are generated at output s0 or s0n, reading the register returns the remaining number of step pulses to be generated. -/w -/w 0 . . . +(2 32 ) 1 table 149: mfc i o register 24 C sd_ch0_steptarget ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 124 / 204 7.3.4.8 register 25 C sd_ch1_steptarget bit description ecat pd i range [unit] 31:0 steps pulses (= distance) to be made for sd_ch1. can be overwritten at any time. when zero, no more step pulses are generated at output s1 or s1n, reading the register returns the remaining number of step pulses to be generated. -/w -/w 0 . . . +(2 32 ) 1 table 150: mfc i o register 25 C sd_ch1_steptarget 7.3.4.9 register 26 C sd_ch2_steptarget bit description ecat pd i range [unit] 31:0 steps pulses (= distance) to be made for sd_ch2. can be overwritten at any time. when zero, no more step pulses are generated at output s2 or s2n, reading the register returns the remaining number of step pulses to be generated. -/w -/w 0 . . . +(2 32 ) 1 table 151: mfc i o register 26 C sd_ch2_steptarget 7.3.4.10 register 27 C sd_ch0_compare bit description ecat pd i range [unit] 31:0 comparison value to compare with actual value of sd_ch0_stepcount. when both are equal and bit 6 in sd_cfg is set, the next step rate as con 1 gured in sd_ch0_nextsr will be assigned and used for sd_ch0_sr. -/w -/w 2 31 . . . +(2 31 ) 1 table 152: mfc i o register 27 C sd_ch0_compare ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 125 / 204 7.3.4.11 register 28 C sd_ch1_compare bit description ecat pd i range [unit] 31:0 comparison value to compare with actual value of sd_ch1_stepcount. when both are equal and bit 6 in sd_cfg is set, the next step rate as con 1 gured in sd_ch1_nextsr will be assigned and used for sd_ch1_sr. -/w -/w 2 31 . . . +(2 31 ) 1 table 153: mfc i o register 28 C sd_ch1_compare 7.3.4.12 register 29 C sd_ch2_compare bit description ecat pd i range [unit] 31:0 comparison value to compare with actual value of sd_ch2_stepcount. when both are equal and bit 6 in sd_cfg is set, the next step rate as con 1 gured in sd_ch2_nextsr will be assigned and used for sd_ch2_sr. -/w -/w 2 31 . . . +(2 31 ) 1 table 154: mfc i o register 29 C sd_ch2_compare 7.3.4.13 register 30 C sd_ch0_nextsr bit description ecat pd i range [unit] 31:0 next accumulation constant that will be written to sd_ch0_steprate at compare event. -/w -/w 0 . . . +(2 32 ) 1 table 155: mfc i o register 30 C sd_ch0_nextsr 7.3.4.14 register 31 C sd_ch1_nextsr bit description ecat pd i range [unit] 31:0 next accumulation constant that will be written to sd_ch1_steprate at compare event. -/w -/w 0 . . . +(2 32 ) 1 table 156: mfc i o register 31 C sd_ch1_nextsr ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 126 / 204 7.3.4.15 register 32 C sd_ch2_nextsr bit description ecat pd i range [unit] 31:0 next accumulation constant that will be written to sd_ch2_steprate at compare event. -/w -/w 0 . . . +(2 32 ) 1 table 157: mfc i o register 32 C sd_ch2_nextsr 7.3.4.16 register 33 C sd_steplength bit description ecat pd i range [unit] 15:0 con 1 gurable step pulse length for sd_ch0 in terms of 25mhz clock cycles. -/w -/w 0 . . . +(2 16 ) 1 31:16 con 1 gurable step pulse length for sd_ch1 in terms of 25mhz clock cycles. -/w -/w 0 . . . +(2 16 ) 1 47:32 con 1 gurable step pulse length for sd_ch2 in terms of 25mhz clock cycles. -/w -/w 0 . . . +(2 16 ) 1 table 158: mfc i o register 33 C sd_steplength note maximum step length: the individual step pulse length t st ep _ p u lse [s] must be lower than the time t st ep [s] between step pulses to actually see step pulses. the condition t st ep _ p u lse < t st ep must be ensured by the application. also refer to section 7.14 for more details and formulas for calculation. 7.3.4.17 register 34 C sd_delay bit description ecat pd i range [unit] 15:0 con 1 gurable step-to-direction delay for sd_ch0 in terms of 25mhz clock cycles. -/w -/w 0 . . . +(2 16 ) 1 31:16 con 1 gurable step-to-direction delay for sd_ch1 in terms of 25mhz clock cycles. -/w -/w 0 . . . +(2 16 ) 1 47:32 con 1 gurable step-to-direction delay for sd_ch2 in terms of 25mhz clock cycles. -/w -/w 0 . . . +(2 16 ) 1 table 159: mfc i o register 34 C sd_delay note step-to-direction delay is the delay between the 1 rst step pulse after a change of the direction. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 127 / 204 7.3.4.18 register 35 C sd_cfg bit description ecat pd i range [unit] 0 0/1 = disable/enable sd_ch0 -/w -/w 1 0 = generate n pulses based on sd_ch0_steptarget register value 1 = continuous mode -/w -/w 2 s0 and s0n step pulse signal polarity -/w -/w 3 d0 and d0n direction signal polarity -/w -/w 4 1 = clears sd_ch0_stepcount -/w -/w 5 reserved -/w -/w 6 use sd_ch0_nextsr for sd_ch0_steprate on compare event -/w -/w 7 reserved -/w -/w 8 0/1 = disable/enable sd_ch1 -/w -/w 9 0 = generate n pulses based on sd_ch1_steptarget register value 1 = continuous mode -/w -/w 10 s1 and s1n step pulse signal polarity -/w -/w 11 d1 and d1n direction signal polarity -/w -/w 12 1 = clears sd_ch1_stepcount -/w -/w 13 reserved -/w -/w 14 use sd_ch1_nextsr for sd_ch1_steprate on compare event -/w -/w 15 reserved -/w -/w 16 0/1 = disable/enable sd_ch2 -/w -/w 17 0 = generate n pulses based on sd_ch2_steptarget register value 1 = continuous mode -/w -/w 18 s2 and s2n step pulse signal polarity -/w -/w 19 d2 and d2n direction signal polarity -/w -/w 20 1 = clears sd_ch2_stepcount -/w -/w 21 reserved -/w -/w 22 use sd_ch2_nextsr for sd_ch2_steprate on compare event -/w -/w 23 reserved -/w -/w table 160: mfc i o register 35 C sd_cfg ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 128 / 204 7.3.5 pwm unit 7.3.5.1 register 36 C pwm_cfg bit description ecat pd i range [unit] 11:0 pwm max count -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w 18:16 pwm ch0 chopper mode see section 7.15 for more details. -/w -/w 19 unused -/w -/w 22:20 pwm ch1 chopper mode see section 7.15 for more details. -/w -/w 23 unused -/w -/w 26:24 pwm ch2 chopper mode see section 7.15 for more details. -/w -/w 27 unused -/w -/w 30:28 pwm ch3 chopper mode see section 7.15 for more details. -/w -/w 31 unused -/w -/w 33:32 pwm alignment for all pwm channels -/w -/w 39:34 unused -/w -/w 47:40 signal polarities for all pwm channels bit 40 = pwm low sides polarity bit 41 = pwm high sides polarity bit 42 = pwm ab pulses polarity bit 43 = pwm b pulses polarity bit 44 = pwm center pulses polarity bit 45 = pwm a pulses polarity bit 46 = pwm zero pulses polarity -/w -/w 47 unused -/w -/w 55:48 bbm low sides. brake before make time in terms of 100mhz clock cycles for low side mosfet control -/w -/w 0 . . . +(2 8 ) 1 63:56 bbm high sides. brake before make time in terms of 100mhz clock cycles for high side mosfet control -/w -/w 0 . . . +(2 8 ) 1 table 161: mfc i o register 36 C pwm_cfg ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 129 / 204 7.3.5.2 register 37 C pwm1 bit description ecat pd i range [unit] 11:0 pwm duty cycle (on time) for pwm1 -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w table 162: mfc i o register 37 C pwm1 7.3.5.3 register 38 C pwm2 bit description ecat pd i range [unit] 11:0 pwm duty cycle (on time) for pwm2 -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w table 163: mfc i o register 38 C pwm2 7.3.5.4 register 39 C pwm3 bit description ecat pd i range [unit] 11:0 pwm duty cycle (on time) for pwm3 -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w table 164: mfc i o register 39 C pwm3 7.3.5.5 register 40 C pwm4 bit description ecat pd i range [unit] 11:0 pwm duty cycle (on time) for pwm4 -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w table 165: mfc i o register 40 C pwm4 7.3.5.6 register 41 C pwm1_cntrshft bit description ecat pd i range [unit] 11:0 shift value for pwm1 to shift pwm1 high side and low side signal edges with respect to the aligned pwm counter. -/w -/w 0 . . . +(2 12 ) 1 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 130 / 204 bit description ecat pd i range [unit] 15:12 unused -/w -/w table 166: mfc i o register 41 C pwm1_cntrshft 7.3.5.7 register 42 C pwm2_cntrshft bit description ecat pd i range [unit] 11:0 shift value for pwm2 to shift pwm2 high side and low side signal edges with respect to the aligned pwm counter. -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w table 167: mfc i o register 42 C pwm2_cntrshft 7.3.5.8 register 43 C pwm3_cntrshft bit description ecat pd i range [unit] 11:0 shift value for pwm3 to shift pwm3 high side and low side signal edges with respect to the aligned pwm counter. -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w table 168: mfc i o register 43 C pwm3_cntrshft 7.3.5.9 register 44 C pwm4_cntrshft bit description ecat pd i range [unit] 11:0 shift value for pwm4 to shift pwm4 high side and low side signal edges with respect to the aligned pwm counter. -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w table 169: mfc i o register 44 C pwm4_cntrshft ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 131 / 204 7.3.5.10 register 45 C pwm_pulse_b_pulse_a bit description ecat pd i range [unit] 11:0 programmable trigger pulse a value with re- spect to the common pwm counter. -/w -/w 0 . . . +(2 12 ) 1 15:12 unused -/w -/w 27:16 programmable trigger pulse b value with re- spect to the common pwm counter. -/w -/w 0 . . . +(2 12 ) 1 31:28 unused -/w -/w table 170: mfc i o register 45 C pwm_pulse_b_pulse_a 7.3.5.11 register 46 C pwm_pulse_length bit description ecat pd i range [unit] 7:0 programmable pulse length for trigger pulse a, b, pwm start, and pwm center. -/w -/w 0 . . . +(2 8 ) 1 table 171: mfc i o register 46 C pwm_pulse_length ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 132 / 204 7.3.6 general purpose i /os 7.3.6.1 register 47 C gpo bit description ecat pd i range [unit] 15:0 gpox output values -/w -/w 31:16 gpox safe state (when emergency input pin mfc_nes = 0 ) -/w -/w table 172: mfc i o register 47 C gpo note bits [31:24] are not available in -es sample devices. 7.3.6.2 register 48 C gp i bit description ecat pd i range [unit] 15:0 gp i x input values r/- r/- table 173: mfc i o register 48 C gp i 7.3.6.3 register 49 C gp i o_conf i g bit description ecat pd i range [unit] 15:0 output enable con 1 guration for the gpox sig- nals disabled = tristated. -/w -/w table 174: mfc i o register 49 C gp i o_conf i g note gp i o_conf i g is not available in -es sample devices. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 133 / 204 7.3.7 dac unit 7.3.7.1 register 50 C dac_val bit description ecat pd i range [unit] 15:0 16 bit dac value which is converted to a pseu- dorandom binary sequence at the dac output pin -/w -/w table 175: mfc i o register 50 C dac_val ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 134 / 204 7.3.8 i rq control block 7.3.8.1 register 51 C mfc i o_ i rq_cfg bit description ecat pd i range [unit] 0 abn encoder unit n-channel event -/w -/w 1 sd_ch0 target reached event -/w -/w 2 sd_ch1 target reached event -/w -/w 3 sd_ch2 target reached event -/w -/w 4 sd_ch0 compare value event -/w -/w 5 sd_ch1 compare value event -/w -/w 6 sd_ch2 compare value event -/w -/w 7 sp i new data available event -/w -/w 8 i 2c new data available event -/w -/w 9 i 2c transmit complete event -/w -/w 10 i 2c new data available event or i 2c transmit complete event -/w -/w 11 watchdog timeout event -/w -/w 12 pwm zero pulse event -/w -/w 13 pwm center pulse event -/w -/w 14 pwm a pulse event -/w -/w 15 pwm b pulse event -/w -/w 16 hv_ot_flag has been set -/w -/w 17 bvout_ot_flag has been set -/w -/w 18 bvout_sc_fl has been set -/w -/w 19 b3v3_sc_flag has been set -/w -/w 22:20 unused/reserved -/w -/w 23 emergency input pin mfc_nes event -/w -/w table 176: mfc i o register 51 C mfc i o_ i rq_cfg note this register is used for masking / enabling the di ? erent i rq sources, which are or-ed together to set the common mfc i o_ i rq output signal. the mfc i o_ i rq is a dedicated package pin of tmc8462, which can be connected to a local application controller. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 135 / 204 7.3.8.2 register 52 C mfc i o_ i rq_flags bit description ecat pd i range [unit] 0 abn encoder unit n-channel event 2 ag r/- r/- 1 sd_ch0 target reached event 2 ag r/- r/- 2 sd_ch1 target reached event 2 ag r/- r/- 3 sd_ch2 target reached event 2 ag r/- r/- 4 sd_ch0 compare value event 2 ag r/- r/- 5 sd_ch1 compare value event 2 ag r/- r/- 6 sd_ch2 compare value event 2 ag r/- r/- 7 sp i new data available event 2 ag r/- r/- 8 i 2c new data available event 2 ag r/- r/- 9 i 2c transmit complete event 2 ag r/- r/- 10 i 2c new data available event or i 2c transmit complete event 2 ag r/- r/- 11 watchdog timeout event 2 ag r/- r/- 12 pwm zero pulse event 2 ag r/- r/- 13 pwm center pulse event 2 ag r/- r/- 14 pwm a pulse event 2 ag r/- r/- 15 pwm b pulse event 2 ag r/- r/- 16 hv_ot_flag r/- r/- 17 bvout_ot_flag r/- r/- 18 bvout_sc_fl r/- r/- 19 b3v3_sc_flag r/- r/- 22:20 unused/reserved -/- -/- 23 emergency input pin mfc_nes event 2 ag r/- r/- table 177: mfc i o register 52 C mfc i o_ i rq_flags note reading this registers clears all 2 ags. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 136 / 204 7.3.9 watchdog 7.3.9.1 register 53 C wd_t i me bit description ecat pd i range [unit] 31:0 watchdog time 32 bit/unsigned 0 = watchdog o ? , > 0 = number of 25mhz clock cycles -/w -/w 0 : : : + (2 32 ) 1 table 178: mfc i o register 53 C wd_t i me 7.3.9.2 register 54 C wd_cfg bit description ecat pd i range [unit] 0 cfg_persistent 0 = the watchdog action ends when the next trigger event occurs 1 = a timeout situation can only be cleared by rewriting wd_t i me -/w -/w 1 cfg_pdi_csn_enable 1 = retrigger by positive edge on pd i _sp i _csn -/w -/w 2 cfg_mfc_csn_enable 1 = retrigger by positive edge on mfc_ctrl_sp i _csn -/w -/w 3 cfg_sof_enable 1 = retrigger by ethercat start of frame -/w -/w 4 cfg_in_edge 0 = retrigger by input condition becoming false 1 = retrigger by input condition becoming true -/w -/w 6:5 unused/reserved -/- -/- 7 cfg_wd_active 1 = signals an active watchdog timeout -/w -/w table 179: mfc i o register 54 C wd_cfg ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 137 / 204 7.3.9.3 register 55 C wd_out_mask_pol bit description ecat pd i range [unit] 23:0 wd_out_pol, polarity for outputs a ? ected by watchdog ac- tion. each bit corresponds to one output line. the polarity describes the output level desired upon watchdog event. -/w -/w 31:24 unused/reserved -/- -/- 55:32 wd_out_mask, each bit corresponds to one output line. 0 = output is not a ? ected 1 = output [i] becomes set to wd_out_pol[i] upon watchdog event. -/w -/w 63:56 unused/reserved -/- -/- table 180: mfc i o register 55 C wd_out_mask_pol note see section 7.19 for the detailed signal mapping of wd_out_mask_pol. 7.3.9.4 register 56 C wd_oe_pol bit description ecat pd i range [unit] 31:0 i /o output enable level for outputs a ? ected by watchdog action. each bit corresponds to one output line. the polarity describes the oe setting desired upon watchdog action (1 = output, 0 = input). -/w -/w table 181: mfc i o register 56 C wd_oe_pol ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 138 / 204 7.3.9.5 register 57 C wd_ i n_mask_pol bit description ecat pd i range [unit] 23:0 wd_ i n_pol, i nput signal levels for watchdog re-triggering. each bit corresponds to one input line. the polarity describes the input level for signals selected by wd_ i n_mask required to re-trigger the watchdog timer. -/w -/w 31:24 unused/reserved -/- -/- 55:32 wd_ i n_mask, each bit corresponds to one input line. 0 = i nput is not selected 1 = i nput i /o[i] must reach polarity wd_ i n_pol[i] to re-trigger the watchdog timer. -/w -/w 63:56 unused/reserved -/- -/- table 182: mfc i o register 57 C wd_ i n_mask_pol note see section 7.19 for the detailed signal mapping of wd_ i n_mask_pol. 7.3.9.6 register 58 C wd_max bit description ecat pd i range [unit] 31:0 peak value reached by watchdog timeout counter. reset to 0 by writing to wd_t i me. r/- r/- 0 : : : + (2 32 ) 1 table 183: mfc i o register 58 C wd_max ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 139 / 204 7.3.10 high voltage status and general control 7.3.10.1 register 59 C hv_ana_status bit description ecat pd i range [unit] 7:0 hv i o_output_hv_detect, bit[i] = 1 = high voltage detected at hv output [i] r/- r/- 15:8 hv_short2gnd_detect, bit[i] = 1 = short to ground detected at hv i o [i-8] r/- r/- 23:16 hv_short2vs_detect, bit[i] = 1 = high voltage detected at hv i o [i-16] r/- r/- 24 hv_ot_flag r/- r/- 25 b3v3_sc_flag r/- r/- 26 bvout_sc_flag r/- r/- 27 bvout_ot_flag r/- r/- 31:28 unused/reserved r/- r/- table 184: mfc i o register 59 C hv_ana_status 7.3.10.2 register 63 C sync1_sync0_event_cnt bit description ecat pd i range [unit] 15:0 sync_out0 event counter value r/- r/- 0 : : : + (2 16 ) 1 31:16 sync_out1 event counter value r/- r/- 0 : : : + (2 16 ) 1 table 185: mfc i o register 63 C sync1_sync0_event_cnt note reading does not clear counters. counters are running all the time and wrap when maximum count is reached. note register 63 can only be read when mapped to the ecat process data ram. i t cannot be read from the mcf ctrl sp i interface. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 140 / 204 7.3.10.3 register 64 C hv i o_cfg bit description ecat pd i range [unit] 7:0 hv_slope_slow with these option bits set to 1, the output slope of the mfc_hv[i] pin can be slowed down. -/w -/w 15:8 hv_weak_h i gh with these option bits set to 1, the high level driver strength of the mfc_hv[i-8] pin can be reduced. -/w -/w 23:16 hv_weak_low with these option bits set to 1, the low level driver strength of the mfc_hv[i-16] pin can be reduced. -/w -/w 27:24 hv_d i ff_ i nput_en with these option bits set to 1, two of the mfc_hv inputs can be combined to a di ? er- ential input pair. bit 24 = 1 = mfc_hv3 & mfc_hv0 bit 25 = 1 = mfc_hv4 & mfc_hv1 bit 26 = 1 = mfc_hv5 & mfc_hv2 bit 27 = 1 = mfc_hv7 & mfc_hv6 -/w -/w 31:28 unused/reserved -/- -/- table 186: mfc i o register 64 C hv i o_cfg note this register can only be accessed from mfc ctrl sp i interface. i t cannot directly be accessed from ecat master interface. nevertheless, the register content can be preloaded from s ii eeprom at startup. therefore, see section 7.4 . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 141 / 204 7.3.10.4 register 65 C buck_conv_cfg bit description ecat pd i range [unit] 1:0 b3v3_saw_freq 3.3v switching regulator switching frequency (nominal values) 0 : 250khz 1 : 125khz 2 : 500khz 3 : 1mhz -/w -/w 3:2 b3v3_fb_ampl 3.3v switching regulator voltage error feedback ampli 1 cation 0 : 100% 1 : 150% 2 : 200% 3 : 50% -/w -/w 5:4 b3v3_fb_cap 3.3v switching regulator dampening of voltage error feedback 0 : 100% 1 : 150% 2 : 200% 3 : 50% -/w -/w 6 b3v3_sc_d i sable 3.3v switching regulator disable cycle-to-cycle overcurrent protection 0 : protection enabled 1 : no protection -/w -/w 7 unused/reserved -/w -/w 9:8 bvout_saw_freq adjustable switching regulator switching fre- quency (nominal values) 0 : 250khz 1 : 125khz 2 : 500khz 3 : 1mhz -/w -/w 11:10 bvout_fb_ampl adjustable switching regulator voltage error feedback ampli 1 cation 0 : 100% 1 : 150% 2 : 200% 3 : 50% -/w -/w ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 142 / 204 bit description ecat pd i range [unit] 13:12 bvout_fb_cap adjustable switching regulator dampening of voltage error feedback 0 : 100% 1 : 150% 2 : 200% 3 : 50% -/w -/w 14 bvout_sc_d i sable adjustable switching regulator disable cycle-to- cycle overcurrent protection 0 : protection enabled 1 : no protection -/w -/w 15 bvout_d i sable disable adjustable switching regulator 0 : switching regulator enabled 1 : switching regulator disabled -/w -/w table 187: mfc i o register 65 C buck_conv_cfg note this register can only be accessed from mfc ctrl sp i interface. i t cannot directly be accessed from ecat master interface. nevertheless, the register content can be preloaded from s ii eeprom at startup. therefore, see section 7.4 . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 143 / 204 7.3.11 application layer control 7.3.11.1 register 66 C al_overr i de bit description ecat pd i range [unit] 0 0 = no override 1 = override al state -/w -/w 7:1 unused/reserved -/- -/- table 188: mfc i o register 66 C al_overr i de note the bit controls override con 1 guration of the 24 mfc i o output ports regarding the output port availability with respect to the actual ethercat slave controller s al state. typically, in an ethercat slave the output ports are only available/active when al state = " op" (operational). i f the override bit is set, the al state is ignored and the mfc i o ports are fully available via the mfc i o control i nterface. the abn functional block, i rq con 1 guration, watchdog block are not a ? ected by this con 1 guration option since they only have input ports/signals. ! this register can only be accessed from mfc i o control i nterface. i t cannot be accessed from ecat master side. the input ports are always readable via the mfc i o control i nterface. when an input port is con 1 gured to be accessed by the ethercat master, it can only be read when the ethercat state machine is in safe-operational state or operational state. when an output port/value is con 1 gured to be controlled by the ethercat master, this is only possible when the ethercat state machine is in operational state because. this is de 1 ned in the ethercat standard. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 144 / 204 7.4 s ii eeprom mfc i o block parameter map this section describes the part of the eeprom content and xml/es i 1 le that is used to con 1 gure the mfc i o block. mfc i o con 1 guration data is automatically loaded at startup from eeprom to the esc parameter ram start- ing at address 0x0580 of the the esc register set. therefore, this con 1 guration data has to be of category 1 . when a category 1 block is present in the eeprom at address 0080 h , the eeprom con 1 guration is auto- matically loaded at power up of the tmc8462. i t is used for setting up the basic tmc8462 ethercat related features. the con 1 guration can later be changed via sp i access to the tmc8462 memory, the memory at address 0580 h corresponds to the beginning of the category data at eeprom address 0084 h . i t can also be used to set up the features of the mfc i o block available via the process data ram. typically, the eeprom content is unique to a speci 1 c slave application and does not change. the required mfc i o functional blocks and their parameters are con 1 gured into the slave controllers ram for use along with sync managers. note the eeprom content starting at address 0084 h to address 0103 h (128 bytes) will be loaded into the ethercat slave controllers parameter memory at address range 0580 h to 05ff h . i f the category is shorter than 128 bytes, only the amount of data speci 1 ed by category data size is copied with the remaining bytes being reset to 0. address in eeprom address in esc ram group function 0080 h - category header (lo) 01 h 0081 h - category header (hi) 00 h 0082 h - category data size in words (lo) 31 h (for the full mfc i o block con 1 g- uration vector) 0083 h - category data size in words (hi) 00 h 0084 h 0580 h crossbar con 1 guration mfc i o00 con 1 guration (see section 7.5 ) 0085 h 0581 h crossbar con 1 guration mfc i o01 con 1 guration 0086 h 0582 h crossbar con 1 guration mfc i o02 con 1 guration 0087 h 0583 h crossbar con 1 guration mfc i o03 con 1 guration 0088 h 0584 h crossbar con 1 guration mfc i o04 con 1 guration 0089 h 0585 h crossbar con 1 guration mfc i o05 con 1 guration 008a h 0586 h crossbar con 1 guration mfc i o06 con 1 guration 008b h 0587 h crossbar con 1 guration mfc i o07 con 1 guration 008c h 0588 h crossbar con 1 guration mfc i o08 con 1 guration 008d h 0589 h crossbar con 1 guration mfc i o09 con 1 guration ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 145 / 204 008e h 058a h crossbar con 1 guration mfc i o10 con 1 guration 008f h 058b h crossbar con 1 guration mfc i o11 con 1 guration 0090 h 058c h crossbar con 1 guration mfc i o12 con 1 guration 0091 h 058d h crossbar con 1 guration mfc i o13 con 1 guration 0092 h 058e h crossbar con 1 guration mfc i o14 con 1 guration 0093 h 058f h crossbar con 1 guration mfc i o15 con 1 guration 0094 h 0590 h crossbar con 1 guration mfc_hv0 con 1 guration 0095 h 0591 h crossbar con 1 guration mfc_hv1 con 1 guration 0096 h 0592 h crossbar con 1 guration mfc_hv2 con 1 guration 0097 h 0593 h crossbar con 1 guration mfc_hv3 con 1 guration 0098 h 0594 h crossbar con 1 guration mfc_hv4 con 1 guration 0099 h 0595 h crossbar con 1 guration mfc_hv5 con 1 guration 009a h 0596 h crossbar con 1 guration mfc_hv6 con 1 guration 009b h 0597 h crossbar con 1 guration mfc_hv7 con 1 guration 009c h 0598 h hv i o con 1 guration slow slope (see section 7.6 ) 009d h 0599 h hv i o con 1 guration weak high 009e h 059a h hv i o con 1 guration weak low 009f h 059b h hv i o con 1 guration di ? erential input 00a0 h 059c h switching regulator con 1 guration 3.3v switching regulator (see sec- tion 7.7 ) 00a1 h 059d h switching regulator con 1 guration adjustable switching regulator 00a2 h 059e h memory block con 1 guration memory block 0 start address low byte (see section 7.8 ) 00a3 h 059f h memory block con 1 guration memory block 0 start address high byte 00a4 h 05a0 h memory block con 1 guration memory block 1 start address low byte 00a5 h 05a1 h memory block con 1 guration memory block 1 start address high byte 00a6 h 05a2 h mfc register con 1 guration enc_mode (w) 00a7 h 05a3 h mfc register con 1 guration enc_status (r) 00a8 h 05a4 h mfc register con 1 guration x_enc (w) 00a9 h 05a5 h mfc register con 1 guration x_enc (r) 00aa h 05a6 h mfc register con 1 guration enc_const (w) 00ab h 05a7 h mfc register con 1 guration enc_latch (r) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 146 / 204 00ac h 05a8 h mfc register con 1 guration sp i _rx_data (r) 00ad h 05a9 h mfc register con 1 guration sp i _tx_data (w) 00ae h 05aa h mfc register con 1 guration sp i _conf (w) 00af h 05ab h mfc register con 1 guration sp i _status (r) 00b0 h 05ac h mfc register con 1 guration sp i _length (w) 00b1 h 05ad h mfc register con 1 guration sp i _t i me (w) 00b2 h 05ae h mfc register con 1 guration i 2c_t i mebase (w) 00b3 h 05af h mfc register con 1 guration i 2c_control (w) 00b4 h 05b0 h mfc register con 1 guration i 2c_status (r) 00b5 h 05b1 h mfc register con 1 guration i 2c_address (w) 00b6 h 05b2 h mfc register con 1 guration i 2c_data_r (r) 00b7 h 05b3 h mfc register con 1 guration i 2c_data_w (w) 00b8 h 05b4 h mfc register con 1 guration sd_ch0_steprate (w) 00b9 h 05b5 h mfc register con 1 guration sd_ch1_steprate (w) 00ba h 05b6 h mfc register con 1 guration sd_ch2_steprate (w) 00bb h 05b7 h mfc register con 1 guration sd_ch0_stepcount (r) 00bc h 05b8 h mfc register con 1 guration sd_ch1_stepcount (r) 00bd h 05b9 h mfc register con 1 guration sd_ch2_stepcount (r) 00be h 05ba h mfc register con 1 guration sd_ch0_steptarget (w) 00bf h 05bb h mfc register con 1 guration sd_ch1_steptarget (w) 00c0 h 05bc h mfc register con 1 guration sd_ch2_steptarget (w) 00c1 h 05bd h mfc register con 1 guration sd_ch0_compare (w) 00c2 h 05be h mfc register con 1 guration sd_ch1_compare (w) 00c3 h 05bf h mfc register con 1 guration sd_ch2_compare (w) 00c4 h 05c0 h mfc register con 1 guration sd_ch0_nextsr (w) 00c5 h 05c1 h mfc register con 1 guration sd_ch1_nextsr (w) 00c6 h 05c2 h mfc register con 1 guration sd_ch2_nextsr (w) 00c7 h 05c3 h mfc register con 1 guration sd_steplength (w) 00c8 h 05c4 h mfc register con 1 guration sd_delay (w) 00c9 h 05c5 h mfc register con 1 guration sd_cfg (w) 00ca h 05c6 h mfc register con 1 guration pwm_cfg (w) 00cb h 05c7 h mfc register con 1 guration pwm1 (w) 00cc h 05c8 h mfc register con 1 guration pwm2 (w) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 147 / 204 00cd h 05c9 h mfc register con 1 guration pwm3 (w) 00ce h 05ca h mfc register con 1 guration pwm4 (w) 00cf h 05cb h mfc register con 1 guration pwm1_cntrshft (w) 00d0 h 05cc h mfc register con 1 guration pwm2_cntrshft (w) 00d1 h 05cd h mfc register con 1 guration pwm3_cntrshft (w) 00d2 h 05ce h mfc register con 1 guration pwm4_cntrshft (w) 00d3 h 05cf h mfc register con 1 guration pwm_pulse_b_pulse_a (w) 00d4 h 05d0 h mfc register con 1 guration pwm_pulse_length (w) 00d5 h 05d1 h mfc register con 1 guration gpo (w) 00d6 h 05d2 h mfc register con 1 guration gp i (r) 00d7 h 05d3 h mfc register con 1 guration gp i o_conf i g (w) 00d8 h 05d4 h mfc register con 1 guration dac_val (w) 00d9 h 05d5 h mfc register con 1 guration mfc i o_ i rq_cfg (w) 00da h 05d6 h mfc register con 1 guration mfc i o_ i rq_flags (r) 00db h 05d7 h mfc register con 1 guration wd_t i me (w) 00dc h 05d8 h mfc register con 1 guration wd_cfg (w) 00dd h 05d9 h mfc register con 1 guration wd_out_mask_pol (w) 00de h 05da h mfc register con 1 guration wd_oe_pol (w) 00df h 05db h mfc register con 1 guration wd_ i n_mask_pol (w) 00e0 h 05dc h mfc register con 1 guration wd_max (r) 00e1 h 05dd h mfc register con 1 guration hv_ana_status (r) 00e2 h 05de h unused unused 00e3 h 05df h unused unused 00e4 h 05e0 h unused unused 00e5 h 05e1 h mfc register con 1 guration sync1_sync0_event_cnt (r) table 189: eeprom parameter map ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 148 / 204 7.5 s ii eeprom mfc i o crossbar mapping the tmc8462 contains a full crossbar. the 24 mfc i o pins (16x low voltage 3.3v mfc i o pins and 8x high voltage mfc i o pins) of the tmc8462 can be freely assigned to any signal coming from or going to the mfc i o functional blocks. without initialization from the s ii eeprom on power up or later via pd i sp i /ecat memory access during operation, all i os are tri-stated. note certain output signals (e.g. pwm signals, dac, ...) generate very short pulses (down to 10ns) which are faster than the slew rate of the hv i o output drivers. i t is still possible to use this con 1 guration, so that the user can evaluate if the application speci 1 c conditions allow to work directly with the hv i o outputs. otherwise external signal conditioning is required. one output signal can be mapped to multiple i o pins, for example to combine the driver strength of multiple pins. the con 1 guration also allows a mapping of multiple pins to one input signal, but usually there is no reason for this con 1 guration. when multiple pins are mapped to the same input signal, a logical or operation is applied to all input pins. each i o pin has a dedicated con 1 guration byte in the s ii eeprom and in the esc s memory space within the esc parameter ram to select the functional mfc i o block signal connected to the physical i o pin: ? mfc i o00 to mfc i o15: s ii eeprom 0084 h to 0093 h / esc parameter ram from 0580 h to 058f h ? mfc_hv0 to mfc_hv7 2 : s ii eeprom: 0094 h to 009b h / esc parameter ram from 0590 h to 0597 h an overview over all con 1 gurable mfc i o block signals is given in table 190 . name function block description direction value dec. value hex. zero none disabled - 0 00 h low none static low output output 1 01 h hgh none static h i gh output output 2 02 h tr i none static tristate (z) output - 3 03 h a abn decoder abn_a signal input 4 04 h an abn decoder abn_an signal (for di ? erential inputs) input 5 05 h b abn decoder abn_b signal input 6 06 h bn abn decoder abn_bn signal (for di ? erential inputs) input 7 07 h n abn decoder abn_n signal input 8 08 h nn abn decoder abn_nn signal (for di ? erential inputs) input 9 09 h sck sp i sp i sck signal output 10 0a h sd i sp i sp i sd i signal input 11 0b h sdo sp i sp i sdo signal output 12 0c h cs0 sp i sp i cs0 signal output 13 0d h 2 mfc_hv0 to mfc_hv7 mfc i o16 to mfc i o23 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 149 / 204 cs1 sp i sp i cs1 signal output 14 0e h cs2 sp i sp i cs2 signal output 15 0f h cs3 sp i sp i cs3 signal output 16 10 h scl i 2 c i 2 c scl signal output 17 11 h sda i 2 c i 2 c sda signal in/out 18 12 h s0 step/direction step output channel 0 output 19 13 h d0 step/direction direction output channel 0 output 20 14 h s1 step/direction step output channel 1 output 21 15 h d1 step/direction direction output channel 1 output 22 16 h s2 step/direction step output channel 2 output 23 17 h d2 step/direction direction output channel 2 output 24 18 h s0n step/direction i nverted step output channel 0 output 25 19 h d0n step/direction i nverted direction output channel 0 output 26 1a h s1n step/direction i nverted step output channel 1 output 27 1b h d1n step/direction i nverted direction output channel 1 output 28 1c h s2n step/direction i nverted step output channel 2 output 29 1d h d2n step/direction i nverted direction output channel 2 output 30 1e h hs0 pwm channel 0 highside signal output 31 1f h ls0 pwm channel 0 lowside signal output 32 20 h hs1 pwm channel 1 highside signal output 33 21 h ls1 pwm channel 1 lowside signal output 34 22 h hs2 pwm channel 2 highside signal output 35 23 h ls2 pwm channel 2 lowside signal output 36 24 h hs3 pwm channel 3 highside signal output 37 25 h ls3 pwm channel 3 lowside signal output 38 26 h pulse_a pwm pwm counter position a pulse output 72 48 h pulse_c pwm pwm counter center position pulse output 73 49 h pulse_b pwm pwm counter position b pulse output 74 4a h pulse_ab pwm pwm counter position a and b pulses output 75 4b h pulse_z pwm pwm counter zero position pulse output 76 4c h gp i 0 gp i o general purpose input 0 signal input 39 27 h gp i 1 gp i o general purpose input 1 signal input 40 28 h gp i 2 gp i o general purpose input 2 signal input 41 29 h ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 150 / 204 gp i 3 gp i o general purpose input 3 signal input 42 2a h gp i 4 gp i o general purpose input 4 signal input 43 2b h gp i 5 gp i o general purpose input 5 signal input 44 2c h gp i 6 gp i o general purpose input 6 signal input 45 2d h gp i 7 gp i o general purpose input 7 signal input 46 2e h gp i 8 gp i o general purpose input 8 signal input 47 2f h gp i 9 gp i o general purpose input 9 signal input 48 30 h gp i 10 gp i o general purpose input 10 signal input 49 31 h gp i 11 gp i o general purpose input 11 signal input 50 32 h gp i 12 gp i o general purpose input 12 signal input 51 33 h gp i 13 gp i o general purpose input 13 signal input 52 34 h gp i 14 gp i o general purpose input 14 signal input 53 35 h gp i 15 gp i o general purpose input 15 signal input 54 36 h gpo0 gp i o general purpose output 0 signal output 55 37 h gpo1 gp i o general purpose output 1 signal output 56 38 h gpo2 gp i o general purpose output 2 signal output 57 39 h gpo3 gp i o general purpose output 3 signal output 58 3a h gpo4 gp i o general purpose output 4 signal output 59 3b h gpo5 gp i o general purpose output 5 signal output 60 3c h gpo6 gp i o general purpose output 6 signal output 61 3d h gpo7 gp i o general purpose output 7 signal output 62 3e h gpo8 gp i o general purpose output 8 signal output 63 3f h gpo9 gp i o general purpose output 9 signal output 64 40 h gpo10 gp i o general purpose output 10 signal output 65 41 h gpo11 gp i o general purpose output 11 signal output 66 42 h gpo12 gp i o general purpose output 12 signal output 67 43 h gpo13 gp i o general purpose output 13 signal output 68 44 h gpo14 gp i o general purpose output 14 signal output 69 45 h gpo15 gp i o general purpose output 15 signal output 70 46 h dac0 dac pseudorandom 1-bit dac signal output 71 47 h table 190: crossbar con 1 guration values the following figure 32 shows the crossbar with an example con 1 guration. all input signals to the mfc i o i ncremental encoder block are connected via external pins. i n this case the 1 rst 6 low voltage mfc i os are ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 151 / 204 used as inputs. no other functional mfc i o block is used in this example. the curly braces behind each mfc i o number contain the required con 1 guration value in decimal numbers according to table 190 . figure 32: mfc i o crossbar example con 1 guration ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 152 / 204 7.6 s ii eeprom mfc i o high voltage i o (hv i o) con 1 guration the 8 hv i o pins have additional con 1 guration options which can be set on power up from the s ii eeprom or later by sp i access to the memory. the 1 rst three con 1 guration bytes (slope slow, weak high, weak low) each have one bit corresponding to one hv output: bit output 0 mfc_hv0 1 mfc_hv1 2 mfc_hv2 3 mfc_hv3 4 mfc_hv4 5 mfc_hv5 6 mfc_hv6 7 mfc_hv7 table 191: slope slow/weak high/weaklow con 1 g slope slow - 0598 h (s ii eeprom: 009c h ) with this option set to 1, the output slope of the hv i o pins can be slowed down. weak high - 0599 h (s ii eeprom: 009d h ) with this option set to 1, the high level driver strength of the hv i o pins can be reduced. weak low - 059a h (s ii eeprom: 009e h ) with this option set to 1, the low level driver strength of the hv i o pins can be reduced. di ? erential i nput enable - 059b h (s ii eeprom: 009f h ) with this option set to 1, two of the hv i o inputs can be combined to a di ? erential input pair. only the lower 4 bits are used to enable four speci 1 c pairs: bit positive input negative input 0 mfc_hv3 mfc_hv0 1 mfc_hv4 mfc_hv1 2 mfc_hv5 mfc_hv2 3 mfc_hv7 mfc_hv6 table 192: di ? erential hv input con 1 guration the crossbar settings of mfc_hv3, mfc_hv4, mfc_hv5 and mfc_hv7 are ignored when they are used as a di ? erential input. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 153 / 204 7.7 s ii eeprom mfc i o switching regulator con 1 guration 3.3v switching regulator - 059c h (s ii eeprom: 00a0 h ) bit output 1:0 saw_freq - switching frequency (nominal values) 0 : 250khz 1 : 125khz 2 : 500khz 3 : 1mhz 3:2 fb_ampl - voltage error feedback ampli 1 cation 0 : 100% 1 : 150% 2 : 200% 3 : 50% 5:4 fb_cap - dampening of voltage error feedback 0 : 100% 1 : 150% 2 : 200% 3 : 50% 6 sc_d i sable - disable cycle-to-cycle overcurrent protection 0 : protection enabled 1 : no protection table 193: con 1 guration bits for 3.3v switching regulator adjustable switching regulator - 059d h (s ii eeprom: 00a1 h ) bit output 1:0 saw_freq - switching frequency (nominal values) 0 : 250khz 1 : 125khz 2 : 500khz 3 : 1mhz 3:2 fb_ampl - voltage error feedback ampli 1 cation 0 : 100% 1 : 150% 2 : 200% 3 : 50% 5:4 fb_cap - dampening of voltage error feedback 0 : 100% 1 : 150% 2 : 200% 3 : 50% 6 sc_d i sable - disable cycle-to-cycle overcurrent protection 0 : protection enabled 1 : no protection ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 154 / 204 bit output 7 d i sable - disable switching regulator 0 : switching regulator enabled 1 : switching regulator disabled table 194: con 1 guration bits for adjustable switching regulator ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 155 / 204 7.8 s ii eeprom mfc i o memory block mapping the mfc registers can be mapped to speci 1 c memory areas to allow ethercat access, so that the data is directly copied between each register and the assigned memory location. this allows the operation with a less powerful application processor or even without an application processor at all in device emulation mode. the registers are dynamically mapped to one of two memory blocks: ? memory block 0 is used for write-registers (data direction: ethercat master -> mfc register) ? memory block 1 is used for read-registers (data direction: mfc register -> ethercat master). the start address of each memory block can be con 1 gured to be anywhere in the process data ram (1000 h to (4fff h -blocksize)). the length of each block depends on the selected registers that are mapped into the block. extra care should be taken that the blocks do not overlap each other, that they do not overlap with other process data in the dpram, and that the memory blocks start addresses are not too close at 4fff h . memory block 0 base address 059f h :059e h (s ii eeprom: 00a3 h :00a2 h ) the start address of the block that all write registers of the mfc are mapped into. address 059f h contains the upper byte of the start address. allowed values: 10 h ...4f h address 059e h contains the lower byte of the start address. allowed values: 00 h ...ff h memory block 1 base address 05a1 h :05a0 h (s ii eeprom: 00a5 h :00a4 h ) the start address of the block that all read registers of the mfc are mapped into. address 059f h contains the upper byte of the start address. allowed values: 10 h ...4f h address 059e h contains the lower byte of the start address. allowed values: 00 h ...ff h when a register is mapped to the ram for ethercat transfer, its memory address depends on the other enabled registers with a lower register number. the start address of any enabled register will be a multiple of 4 bytes from the start address of the memory block. between registers that are not a multiple of 4 bytes, a padding gap is left that is not transferred. for example if a 2 byte register, a 8 byte register a 1 byte register and a 4 byte register are enabled in a memory block starting at 2000 h , the memory is used as shown in this table: register end address start address reg. 1 (2 byte) 2001 h 2000 h padding 2003 h 2002 h reg. 2 (8 byte) 200b h 2004 h reg. 3 (1 byte) 200c h 200c h padding 200f h 200d h reg. 4 (4 byte) 2013 h 2010 h table 195: register mapping example for the actual register sizes please refer to table 124 in section 7.2 . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 156 / 204 7.9 s ii eeprom mfc i o register con 1 guration all mfc registers are accessible via the mfc i o control sp i i nterface . alternatively they can be mapped into the esc s process data ram to allow access via ethercat. i n this case the mapped registers can only be written by the ethercat master. but they can still be read via mfc i o control sp i i nterface. the transfer of all enabled registers is performed in one access. to enable the data update at certain times only, a shadow register is used for every mfc register. the exact point in time when the actual data transfer occurs (from the shadow register into a write register or from a read register into the shadow register) is based on the chosen trigger source. there is one con 1 guration byte in the s ii eeprom (and esc parameter ram respectively) for each mfc block register. the con 1 guration for all registers has the same options: bit description 3:0 trigger source 4 enable ram transfer 0 : disabled , register access only from mcu via mfc ctrl sp i 1 : enabled , read and write access via ethercat, readable by mcu via mfc ctrl sp i 7:5 unused table 196: register con 1 guration byte trigger source hex. trigger source name description 0 h trigger always shadow register is transparent 1 h sync0 signal distributed clocks sync pulse 0 (0->1) 2 h sync1 signal distributed clocks sync pulse 1 (0->1) 3 h latch0 signal distributed clocks latch input 0 (0->1) 4 h latch1 signal distributed clocks latch input 1 (0->1) 5 h ethercat start of frame (sof) start of frame on ethercat bus 6 h ethercat end of frame (eof) end of frame on ethercat bus 7 h pd i sp i ncs=0 (chip select) falling edge on pd i _sp i _csn pin 8 h pd i sp i ncs=1 (chip deselect) rising edge on pd i _sp i _csn pin 9 h mfc sp i ncs=0 (chip select) falling edge on mfc_ctrl_sp i _csn pin a h mfc sp i ncs=1 (chip deselect) rising edge on mfc_ctrl_sp i _csn pin b h trigger before register is handled before data is copied to/from ram by memory bridge c h trigger after register was handled after data is copied to/from ram by memory bridge d h trigger on pwm counter = 0 transfer at the zero pulse of the mfc pwm unit e h trigger never no data is transferred, can be used for debugging f h trigger always shadow register is transparent table 197: trigger source descriptions ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 157 / 204 7.10 mfc i o es i /xml con 1 guration block this example shows the part of the es i /xml con 1 guration 1 le for ethercat slaves used to con 1 gure the mcf i o block directly out of the eeprom (at power-up or reset). therefore, the con 1 guration block must be classi 1 ed as category 1 information within the eeprom. another way to con 1 gure the mfc i o block is to directly write via pd i or ecat interface to the ethercat registers at 0x0580 to 0x05e1 (esc parameter ram). an easy way to generate the con 1 guration data string that is used in this xml structure is to use the wizard included in the tmcl- i de. see also section es i con 1 guration wizard . 1 < eeprom > < bytesize > 2048 3 5 configdata > 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 7 9 < category > 11 < catno >1 < data > 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000000 17 19 figure 33: mfc i o es i /xml con 1 guration block note the zeros in the example above are just placeholders and must be adapted to the respective con 1 guration. see the available application notes and examples on www.trinamic.com for more information. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 158 / 204 7.11 mfc i o i ncremental encoder block this function block provides input pins for incremental encoder signals (two quadrature signals and one index signal) with di ? erential option. i t has a large range of resolution settings, allowing the use of many di ? erent encoders without requiring extra calculations. figure 34: mfc i o i ncremental encoder unit encoder block con 1 guration con 1 guration of the i ncremental encoder block is done via the enc_mode register . polarities, index event handling, clear and latch options, and prescaler mode can be con 1 gured. n event flag the lsb in the enc_status register shows that an n event has occurred since the last read access to this register. the 2 ag is cleared on a read access. encoder constant the encoder constant enc_const is added to or subtracted from the encoder counter on each polarity change of the quadrature signals ab of the incremental encoder. the encoder constant enc_const represents a signed 1 xed point number (16.16) to facilitate the generic adaption between motors and encoders. i n decimal mode, the lower 16 bits represent a number between 0 and 9999. for stepper motors equipped with incremental encoders the 1 xed number representation allows very comfortable parametrization. additionally, mechanical gearing can easily be taken into account. negating the sign of enc_const allows inversion of the counting direction to match motor and encoder direction. the encoder constant can be con 1 gured in the enc_const register . examples: ? encoder factor of 1.0: enc_const = 0x0001.0x0000 = factor.fract i on ? encoder factor of -1.0: enc_const = 0xffff.0x0000 this is the two s complement of 0x00010000. i t equals (2 16 -(factor+1)).(2 16 -fract i on) ? decimal mode encoder factor 25.6: enc_const = 00025.6000 = 0x0019.0x1770 = factor.dec i mals ? decimal mode encoder factor -25.6: enc_const = 0xffe6.4000 = 0xffe6.0x0fao. this equals (2 16 -(factor+1)).(10000-dec i mals) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 159 / 204 encoder position the encoder counter enc_x holds the current encoder position ready for read out. di ? erent modes concerning handling of the signals a, b, and n take into account active low and active high signals as found with di ? erent types of encoders. the current encoder position can be read from mfc i o register 3 . the encoder position can also be overwritten and set to a speci 1 c value. the current encoder position can be written to mfc i o register 2 . latched encoder position when either clr_cont or clr_once are set in the enc_mode register , the current encoder position from enc_x is latched into mfc i o register 5 on an active n event. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 160 / 204 7.12 mfc i o sp i master block the sp i master unit provides an interface for up to four sp i slaves with a theoretically unlimited datagram length using multiple accesses. figure 35: block structure of sp i master unit the basic con 1 guration requires setting the sp i frequency/bit length, the datagram length and the sp i mode (clock polarity and phase). extended settings are a special start-of-transmission trigger linked to the pwm unit, the bit order, selection of one of the four sp i slaves and datagram length extension. sp i _rx_data C received data this register contains the received datagram after an sp i transfer. for sp i transfers with less than 64 bit, the upper bits of this register are unused. sp i _tx_data C data to transmit the data to be sent is written to this register. unless con 1 gured di ? er- ently in sp i _conf bits 10..8, writing to this register starts the sp i transfer. for sp i transfers with less than 64 bit, the upper bits of this register are unused. sp i _conf C sp i block con 1 guration ? bit 15 is the trigger bit that can be selected as transmission start trigger (see below). ? bits 10..8 allow a con 1 guration when the data transmission should start, they are interpreted as a 3 bit number: C i n the reset con 1 guration 0, the transmission always starts when data is written to the sp i _tx register. C the settings 1 to 5 link the start of the transmission to the pwm unit, allowing synchronization between the pwm cycle and for example a sp i adc for current measurement. the trigger sources are the 1 ve pwm_pulse signals that are also available on the mfc i o crossbar. please refer to section 7.15 for details about these pulses. C setting 7 is a single shot trigger that starts only one transmission when bit 15 of sp i _conf is written to 1. ? bit 6 and 5 de 1 ne the clock polarity and phase of the sp i signals which de 1 ne what the idle state of the sck signal is and when output data is changed and when input data is sampled. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 161 / 204 clock polarity clock phase sp i mode mos i change m i so sample 0 0 0 sck falling edge sck rising edge 0 1 1 sck rising edge sck falling edge 1 0 2 sck rising edge sck falling edge 1 1 3 sck falling edge sck rising edge table 198: sp i mode con 1 guration ? bit 4 reverses the bit order in the transmission, the least signi 1 cant bit of sp i _tx_data (bit 0) is transmitted 1 rst, the least signi 1 cant bit of sp i _rx_data is the 1 rst received bit, the most signi 1 cant bit of sp i _tx_data is transmitted last and the most signi 1 cant bit of sp i _rx_data is the last bit received. ? bit 3 can be used for datagrams longer than 64 bit. with this bit set, the chip select line is held low after the transmission, allowing more transmissions in the same datagram. before the last transmission, this bit must be set to 0 again so that the chip select line goes high afterwards, ending the datagram. ? bits 1 and 0 de 1 ne which chip select line (which slave) is used for the next transmission. sp i _status C sp i transfer status bit 0 of this register is the ready indicator for the sp i master unit. when this bit is set, a new transfer can be started. when this bit is 0 and the start of a new transfer is triggered, the trigger is ignored, the currently active transfer is 1 nished but the new transfer is not started. sp i _length C sp i datagram length this register de 1 nes the sp i datagram length in bits. any length from 1 to 64 bits is possible. sp i datagram length (bits) = sp i _length+1 sp i _t i me C sp i bit duration this register de 1 nes the bit length and thus the sp i clock frequency. the duration of one sp i clock cycle can be calculated as t sck = (4+(2*sp i _t i me))/25mhz = (4+(2*sp i _t i me))*40ns, the sp i clock frequency is f sck = 25mhz/(4+(2*sp i _t i me)). the delay between the falling edge of csn (becoming active) and the 1 rst sck edge and the last sck edge and the rising edge of csn is always a half sck clock cycle (t sck /2). 7.12.1 sp i examples tmc262 on sp i channel 0 this example shows the con 1 guration of the sp i master unit for a tmc262 as sp i slave 0 and the transfer of data to the tmc262 s drvconf register. 1. use 3.125 mhz sp i clock (25mhz/(4+(2*2))) = (25mhz/8) spi_time <= 0x02 2. use 20 bit datagrams spi_length <= 0x13 3. start on tx write, sp i -mode 3, msb 1 rst, single datagrams, slave 0) spi_conf <= 0x0060 4. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 162 / 204 5. write data into tx register (e.g. tmc262 drvconf register, all 64bit are shown) spi_tx_data <= 0x00000000000ef010 6. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 7. read data from rx register rxdatagram = spi_rx_data chain of 10 74xx595 shift registers used as 80 digital outputs (good example) this example shows the transmission of a longer datagram, in this case 80 bits that are shifted into a chain of 74xx595 shift registers. the ncs of the sp i interface can be used as the storage clock of the 74xx595 to transfer the contents of the shift register into the storage register. the data that should be sent is 0x5555aaaa5555aaaa55aa. i t is recommended to split the data into two chunks of 40 bits each: 0x5555aaaa55 and 0x55aaaa55aa. con 1 guration and 1 rst transmission 1. use 6.25 mhz sp i clock (25mhz/(4+(2*0))) = (25mhz/4) spi_time <= 0x00 2. use a 40 bit datagram spi_length <= 0x28 3. start on tx write, sp i -mode 3, msb 1 rst, keep cs low, slave 0) spi_conf <= 0x0068 4. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 5. write data for the 1 rst 64 outputs into tx register spi_tx_data <= 0x5555aaaa55 6. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 7. start on tx write, sp i -mode 3, msb 1 rst, drive cs high at the end, slave 0) spi_conf <= 0x0060 8. write data for the last 16 outputs into tx register spi_tx_data <= 0x55aaaa55aa 9. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) next transmission with inverted data 1. start on tx write, sp i -mode 3, msb 1 rst, keep cs low, slave 0) spi_conf <= 0x0068 2. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 3. write data for the 1 rst 40 outputs into tx register spi_tx_data <= 0xaaaa5555aa 4. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 5. start on tx write, sp i -mode 3, msb 1 rst, drive cs high at the end, slave 0) spi_conf <= 0x0060 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 163 / 204 6. write data for the last 40 outputs into tx register spi_tx_data <= 0xaa5555aa55 7. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) chain of 10 74xx595 shift registers used as 80 digital outputs (bad example) this bad example is the same as the previous one but with the non-recommended datagram split of 64 bits + 16 bit. this requires more communication since not only the sp i _conf register needs to be changed between the sp i _tx_data writes but also the sp i _length register changes every time. con 1 guration and 1 rst transmission 1. use 6.25 mhz sp i clock (25mhz/(4+(2*0))) = (25mhz/4) spi_time <= 0x00 2. use a 64 bit datagram spi_length <= 0x3f 3. start on tx write, sp i -mode 3, msb 1 rst, keep cs low, slave 0) spi_conf <= 0x0068 4. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 5. write data for the 1 rst 64 outputs into tx register spi_tx_data <= 0x5555aaaa5555aaaa 6. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 7. use a 16 bit datagram (remaining outputs) spi_length <= 0x0f 8. start on tx write, sp i -mode 3, msb 1 rst, drive cs high at the end, slave 0) spi_conf <= 0x0060 9. write data for the last 16 outputs into tx register spi_tx_data <= 0x55aa 10. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) next transmission with inverted data 1. use a 64 bit datagram spi_length <= 0x3f 2. start on tx write, sp i -mode 3, msb 1 rst, keep cs low, slave 0) spi_conf <= 0x0068 3. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) 4. write data for the 1 rst 64 outputs into tx register spi_tx_data <= 0xaaaa5555aaaa5555 5. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 164 / 204 6. use a 16 bit datagram (remaining outputs) spi_length <= 0x0f 7. start on tx write, sp i -mode 3, msb 1 rst, drive cs high at the end, slave 0) spi_conf <= 0x0060 8. write data for the last 16 outputs into tx register spi_tx_data <= 0xaa55 9. wait until sp i -master is ready while (spi_status & 0x01 != 0x01) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 165 / 204 7.13 mfc i o i 2c master block the tmc8462 i 2c master allows accessing i 2c slaves by writing and reading control and data registers instead of needing to take care of timing or even bit-banging through the gp i o block. figure 36: block structure of sp i master unit i 2c_t i mebase C bit duration in s this register determines the i 2c clock frequency by setting the duration of a single bit. a setting of 0 disables communication, a setting of 1 results in bit duration of 1 s, the maximum setting of 255 results in a bit duration of 255 s. i 2c_control C command register there are 6 commands that allow full control of the i 2c master block. each command is represented by a single bit in this register. command byte bit in register command 0x20 5 send start condition (also repeated start) 0x10 4 send stop condition 0x08 3 send address (content of address register), incl. r/nw bit 0x04 2 send data (content of data register) 0x02 1 receive data and send ack 0x01 0 receive data and send nack table 199: i 2c control commands i 2c_status C status register the status bits show the current transmission status either alone or in a combination of multiple bits. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 166 / 204 status bit description 7 error flag 6 not acknowledge received/sent 5 acknowledge received/sent 4 write to slave mode 3 read from slave mode 2 transmit address mode 1 repeated start condition sent 0 start condition sent table 200: i 2c status register bits bits 0 and 1 are set after command 0x20 was successfully executed, either if the i 2c bus was idle or a start condition already has been sent. a combination of bits 2 to 6 indicates completion of an address or data cycle. bit 7 indicates an error during transmission. a stop condition should be sent to return to the idle state. status byte status 0x00 i dle 0x01 start sent 0x02 repeated start sent 0x34 write address ack 0x2c read address ack 0x54 write address nack 0x4c read address nack 0xe4 address error 0x48 read data ack sent 0x28 read data nack sent 0x30 write data ack 0x50 write data nack 0xf0 write data error 0xff general error table 201: i 2c status overview i 2c_addr C address register with r/nw bit this register contains the 7 bit address of the i 2c slave and the single r(ead)/n(ot)w(rite) bit. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 167 / 204 bit 7 6 5 4 3 2 1 0 function a6 a5 a4 a3 a2 a1 a0 r/nw table 202: i 2c addres register i 2c_data_r C data register for received data after a read command, this register contains the last read data byte. i 2c_data_w C data register for data to transmit the data byte that should be sent with the next write command is written to this register. basic usage an usual communication cycle is done by the following steps 1. set the bit duration in s in the i 2c_t i mebase register (only required as con 1 guration after reset or if a di ? erent speed is required). 2. write 0x20 (send start condition) to the i 2c_control register. 3. write the slave address and the r/nw bit to the i 2c_addr register. 4. write 0x80 (send address) to the i 2c_control register. 5. depending on the r/nw bit, either ? write 0x01 (receive data and send nack) or 0x02 (receive data and send ack) to i 2c_control to receive data and send nack or ack. ? read the data from the i 2c_data_r register. or ? write data to the i 2c_data_w register. ? write 0x04 (send data)to i 2c_control to send the data. this can be repeated as long as it is necessary. 6. write 0x10 (send stop condition) to the i 2c_control register. a repeated start condition, as it is required for slaves like eeproms, can be sent like the regular start condition by writing 0x20 to the i 2c_control register at any required time. 7.13.1 i 2c example this example shows reading from an 24lc64 i 2c eeprom. the standard i 2c address is con 1 gurable from 0x50 to 0x57 with 3 address pins. the address 0x50 is used for this example. the memory uses 13 bit addresses, so two memory address bytes are used. the memory address 0x1234 is used for this example. 1. set i 2c clock to 100khz (10s) i2c_timebase <= 0x0a 2. send start condition i2c_control <= 0x20 3. write the slave address and the nw bit ((0x50 ? 1) + 0 = 0xa0) i2c_addr <= 0xa0 4. send address i2c_control <= 0x80 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 168 / 204 5. write upper byte of the memory address i2c_data_w <= 0x12 6. send data i2c_control <= 0x04 7. write lower byte of the memory address i2c_data_w <= 0x34 8. send data i2c_control <= 0x04 9. send repeated-start condition i2c_control <= 0x20 10. write the slave address and the r bit ((0x50 ? 1) + 1 = 0xa1) i2c_addr <= 0xa1 11. command: receive data and send ack i2c_control <= 0x02 12. read the data databyte <= i2c_data_r the last two steps can be repeated as long as it is necessary, for the last byte send a nack instead: 13. command: receive data and send nack i2c_control <= 0x01 14. read the data databyte <= i2c_data_r 15. write 0x10 (send stop condition) to the i 2c_control register. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 169 / 204 7.14 mfc i o step and direction block the mfc i o step & direction block allows for generation of de 1 ned step pulse frequencies along with a direction signal. this is done by writing an accumulation constants to a register. toggle of the msb of the accumulation register value generates an internal step pulse of one internal clock cycle. the direction signal is the msb of the accumulation constant. therefore, the sign of the accumulation constant de 1 nes the direction signal polarity. the step-to-direction timer (stp2d i r) takes care of possible external signal delay paths by programmable delay of the 1 rst step after write of accumulation constant. the pulse stretcher forms step and direction pulses of programmable length for adaption to external signal paths. the step direction unit can either run in free running mode just generating step pulses with programmed frequency. alternatively, is can generate a de 1 ned number of step pulses with programmed frequency. an interrupt output signal i rq target_reached indicates the reached target count of step pulses. tmc8462 has three independent step and direction channels. figure 37: block structure of the mfc i o step and direction block step & direction signal timing write to the accumulation constant register starts step pulse generation. the 1 rst step pulse occurs after a time t st ep 1 st . following step pulses come after each t st ep . the pulse length of the step pulses is t st ep _ p u lse . on change of direction by writing the accumulation constant with a constant of di ? erent sign, the 1 rst step pulse after write occurs after t st p 2 dir . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 170 / 204 figure 38: step & direction signal timing parameter value description / function comment f clk [hz] 25 mhz clock frequency of step direction unit clock frequency of the step direction unit t clk [s] 40 ns clock period length t clk = 1 =f clk f st ep [hz] f st ep = ( f clk = 2 32 ) ( sd _ chx _ st ep rat e ) step frequency, pro- grammed via step rate accumulation constant sd_chx_steprate max. f st ep [hz] 12.5 mhz theoretical maximum value for f st ep . usable step fre- quency depends on step pulse length con 1 guration. t st ep [s] t st ep = 1 =f st ep time between steps t st ep _ p u lse [s] t st ep _ p u lse = ( sd _ st ep _ len gt h + 1) =f clk step pulse length must be lower than time between step pulses! t st ep _ p u lse < t st ep d i r d i r = 0 C > positive direction, d i r = 1 C > negative direction, direction is depending on sign of step rate register sd_chx_steprate where the step rate register is 2th complement direction signal, depending of step rate (sr) parameter, d i r = 0 if sr > 0 or sr = 0, d i r = 1 if sr < 0 t st ep 1 st [s] time to 1st step pulse since wr=0 with t st ep 1 st = 2 32 =sd _ chx _ st ep rat e t clk +( sd _ delay + 1) t clk + (2 t clk ) time between write until the 1 rst step pulse occurs t st ep 1 stw r [s] time to 1 rst step pulse since wr=0 step delay plus 1 internal clock plus 2 clock cycles to pulse length i nternal processing adds an delay table 203: step and direction unit parameters ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 171 / 204 step rate accumulation constant the step direction accumulation constant determines the time t st ep between two successive step pulses C this is actually the step rate. each internal pwm clock accumulates an accumulator according to a = a + c with the accumulator constant c . toggle of the msb of the accumulator register a triggers a step pulse. with this principle, the step frequency is smarter adjustable compared to a simple frequency divider. writing c = 0 clears the accumulator and stops the step pulse generation. the step pulse frequency calculates as f st ep = ( f clk = 2 32 ) c . step counter the step counter counts the number of steps, taking the direction into account. this is a read only register. for initialization to zero a con 1 guration bit within the step direction con 1 guration register hast to be written. step target the step target de 1 nes the number of steps to be made for the step mode until stop. this register can be overwritten at any time. when the number of steps has been made, the unit stops outputting s/d pulses. when read, it gives the remaining numbers that must still be made. step compare this register holds a compare value in numbers of step pulses. i n target mode, the number of steps to be made is con 1 gured in this register. depending on the motor s pole count and the microstep resolution, the numbers of steps represent a certain distance. next step rate the next step rate register contains a value of the same format as the step rate register. this value is automatically written into the step rate register after a successful compare of the step compare value and the actual step counter. this way, simple motion pro 1 les can be realized. step length the duration of the step pulse C the step length C signal is programmable for adaption to external power stages. note maximum step length: the step pulse length t st ep _ p u lse must be lower than the time t st ep between step pulses to actually see step pulses at the outputs. the condition t st ep _ p u lse < t st ep must be ensured by the application. step-to-direction delay the delay between the 1 rst step pulse after a change of the direction is pro- grammable for adaption to external power stages to take external delay paths into account. step direction unit con 1 guration the step direction con 1 guration de 1 nes the mode of operation (continuous or 1 nite number of step pulses), polarity of step pulse signal and direction signal. one bit is for zeroing of step pulse counter. on bit is for enabling and disabling of the step pulse unit and compare mode. i nterrupt output signal an i rq signal target_reached of a single clock pulse length indicates that a certain target position has been reached reached in terms of step counts. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 172 / 204 7.15 mfc i o pwm block the mfc i o block of tmc8462 o ? ers a 4-channel pulse width modulation (pwm) block including a pro- grammable brake before make (bbm) unit and selection of di ? erent pwm modes. both high side and low side control signals are available as separate outputs. a single pwm counter gener- ates the four synchronous pwm signals. the con 1 gurable maximum count de 1 nes the pwm frequency. left aligned pwm, centered pwm, and right aligned pwm is selectable. the bbm timing is individually programmable for high side and low side. fixed pulses are available for triggering of adcs or triggering interrupts of a cpu. additional programmable trigger output signals are available. signal pulse_zero indicates a start of a new pwm cycle and pulse_center the center of a pwm cycle. both are 1 xed. the two programmable signals pulse_a and pulse_b are for advanced adc triggering. the signal pulse_ab is the logical or of pulse_a and pulse_b. the polarities of the high side, low side, and trigger signals of the pwm unit are programmable. figure 39: block structure of the mfc i o pwm block parameter value description / function comment f clk [hz] 100 mhz clock frequency of pwm unit f clk = 1 =t clk t clk [s] 10 ns clock period length t clk = 1 =f clk max. t p w m [s] 40.96 us length of pwm period tp w m = t clk (1+ p w m _ m axcn t ) maximum t p w m with maxi- mum pwm resolution of 12 bit. min. f p w m [hz] 24.414 khz pwm frequency = 1 =t p w m minimal pwm frequency with maximum pwm resolu- tion of 12 bit. t p u lse _ len gt h length of trigger pulses with t p u lse _ len gt h = p u lse _ len gt h t clk pulse length is adjustable t clk = 10 ns ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 173 / 204 t bbm brake before make time t bbm with tbbm _ h = bbm _ h t clk tbbm _ l = bbm _ l t clk i ndividually programmable for high side and low side due to di ? erent timing requirements, especially when using pmos @ high side and nmos @ low side table 204: pwm unit parameters pwm_maxcnt con 1 guration this con 1 guration can be found in the pwm_cfg register . i t de 1 nes the number of counts per pwm cycle for three pwm units. this determines the length t p w m of each pwm cycle respectively the pwm frequency f p w m . i t is programmable for adjustment of the pwm frequency f p w m . pwm_chopmode con 1 guration this con 1 guration can be found in the pwm_cfg register . i t selects the chopper mode of the 4 pwm channels. each channel can be con 1 gured individually. the following table gives the available chopper modes. selection chopper high side low side function 000 no o ? o ? no chopper, all o ? 001 no o ? on no chopper, ls permanent on 010 no no o ? no chopper, hs permanent on 011 no o ? o ? no chopper, all o ? , not used 100 no o ? o ? no chopper, all o ? , not used 101 yes o ? pwm chopper ls, hs o ? 110 yes pwm o ? chopper hs, ls o ? 111 yes pwm not pwm chopper hs and ls complementary, brake-before-make is handled by programmable bbm unit table 205: pwm modes ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 174 / 204 figure 40: pwm chopper modes pwm alignment con 1 guration this con 1 guration can be found in the pwm_cfg register . i t determines the alignment of the 4 pwm units. the alignment can be programmed left aligned, centered, or right aligned. all 4 channels use the same con 1 guration. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 175 / 204 figure 41: pwm timing (centered pwm) figure 42: pwm timing (left aligned pwm) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 176 / 204 figure 43: pwm timing (right aligned pwm) pwm polarity con 1 guration this con 1 guration can be found in the pwm_cfg register . the pwm signals of the 4 channels are of positive logic. logical one level means on and logical zero level means off. depending on the mosfet drivers, switching on a mosfet might require an inverted logical level. the polarity con 1 guration determines the switching polarities for the high side mosfets and switching polarities for the low side mosfets. bbm con 1 guration this con 1 guration can be found in the pwm_cfg register . to avoid cross conduction of the half bridges the brake before make (bbm) timing is programmable. i n most cases the same bbm time is su z cient for both low side and high side. the bbm time should be programmed as short as possible and as long as necessary. a too long bbm time causes conduction of the bulk diodes of the power mosfets and that causes higher power dissipation. i n case of using pmosfets for high and nmosfets for low side with asymmetric switching characteristics, it might be advantageous to program di ? erent bbm_h and bbm_l times. the bbm_l is the time from switch o ? the high side to switch on the low side in terms of clock cycles. the bbm_l is common for all 4 high side power mosfets. the bbm_h is the time from switch o ? the low side to switch on the high side in terms of clock cycles. the bbm_h is common for all 4 low side power mosfets. figure 44: pwm bbm timing ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 177 / 204 pwm value together with the programmed pwm counter length, the pwm values determine the pwm duty cycle. the pwm duty cycle is individually programmable for each of the 4 pwm channels. trigger pulses a and b con 1 guration the positions of the trigger pulses a and b are programmable within the pwm cycle. these pulses can be used for di ? erent purpose, e.g., to trigger adc sampling at a speci 1 c point in time. trigger pulse length con 1 guration the length of pulse_a and pulse_b and the 1 xed trigger pulses pulse_center and pulse_zero is programmable in terms of clock cycles. asymmetric pwm con 1 guration to realize a wider time window between pwm switching events that are close to each other, an asymmetric pwm shift can be programmed individually for each pwm channel. this leaves the pwm duty cycles unchanged. i t is useful for current measurement with sense resistors at the bottom of the mosfet half bridges. figure 45: centered pwm with pwm channel 2 shifted from center (example showing only 3 pwm channels) ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 178 / 204 7.16 mfc i o dac block the dac block generates a digital signal based on a 16 bit pseudo random number generator (prng). a pseudo random number (prn) is compared to the desired output value and a the output is set to 1 if the prn is lower than the output value. the prn generator is clocked with 100mhz, which results in a period length of 655.36s. the output signal can be 1 ltered with a simple rc lowpass. mfc i o[x] 10k 100nf out figure 46: rc 1 lter for dac output with example values note the high voltage outputs are not able to output this signal properly as their slew rate does not allow 10ns pulses. this will lead to voltage levels that don t correspond with the set value. i t is recommended to use the dac block only with the low voltage outputs. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 179 / 204 7.17 mfc i o general purpose i o block tmc8462 has 16 general purpose i o lines that can be freely con 1 gured and used via the 24 mfc i o low voltage and high voltage pins. the general purpose i o signals can be used for indicator leds, switch inputs, and even for relays or small dc motors on the hv i o pins. when con 1 gured as an output signal, a safe state for each signal is available that is set on the pin in case the emergency state is triggered using mfc_nes. figure 47: block structure of gp i o unit after reset, all signals are con 1 gured as an input and present a hi-z state on the gp i o pin they are mapped to. when a signal should be used as an input signal, no further con 1 guration is required after reset, the signal state can be read directly from the gp i register ( 7.3.6.2 ). to con 1 gure a signal as an output, a 1 bit must be written to the signal position in the gp i o_conf i g register ( 7.3.6.3 ). afterwards, the signal can be controlled via the lower 16 bits of the gpo register ( 7.3.6.1 ). the upper 16 bits of the gpo register represent the state in case the emergency state is triggered. gpo (31..16) gpo (15..0) gp i o_conf i g mfc_nes gpo signal comment x x 0 x hi-z reset state x 0 1 1 0 normal operation x 1 1 1 1 normal operation 0 x 1 0 0 emergency state safe output 1 x 1 0 1 emergency state safe output table 206: gpo signal output states ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 180 / 204 7.18 mfc i o i rq block the mfc_ i rq output signal is driven by the mfc i o i rq block and can be used to indicate various events of the mfc i o block. the i rq unit uses two registers to con 1 gure certain i rq trigger events and to check the i rq source when the mfc_ i rq has been triggered. figure 48: block structure of the mfc i o i rq block i rq mask register the i rq mask register allows to enable/disable certain i rq trigger events of the mfc i o block. i rq flags register this register can be read out after the i rq was set to identify the i rq source (especially when more than one i rq source was masked). reading out clears this register. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 181 / 204 7.19 mfc i o watchdog block general function the watchdog timer allows monitoring of external signals, or monitoring of ethercat activity. a certain condition can be chosen for retriggering the watchdog, i.e. a certain input signal constellation. i n case this constellation does not occur at least once within a pre-programmable time period, the watchdog timer will expire and will trigger a certain watchdog action. to avoid static reset of the watchdog, the watchdog input condition is edge sensitive, i.e. it becomes reset when the condition goes active respectively goes inactive. once the watchdog expires, the watchdog safety circuitry becomes active. this action can bring i /o lines into a certain state, in order to allow the system to return to a known, safe condition. therefore, all i /o lines are directly mapped to the gp i o ports of the chip, so that they perform independently of the actually con 1 gured peripheral con 1 guration. the watchdog action can be chosen to remain active continuously, until it becomes reset by a watchdog re-con 1 guration, or it can be programmed to return to normal operation state, once the selected condition becomes true again. i n an optional use case, the watchdog timer can be used to measure the maximum delay in between of the occurrence of certain input conditions, in between of sp i frames, etc. the watchdog unit 1 nds itself between the mfc i o crossbar and the i o pads as shown in figure 49 . thus, the watchdog monitors the 24 mfc i oxx signals. depending on the crossbar mapping these signals are either inputs or outputs. their logical function depends on the crossbar mapping to/from the mfc i o functional sub-blocks. figure 49: logical position of the mfc i o watchdog unit between crossbar and mfc i oxx pins ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 182 / 204 watchdog register set once initialized, the watchdog timer monitors the application for activity and allows setting of pre-programmed i /o patterns, in case the time limit is expired without activity. i n order to allow tuning of this time limit, the maximum time between two trigger events becomes measured. this function also allows delay time measurement for input channels (i.e. when no watchdog action is chosen). the watchdog timeout counter starts from zero up to wd_t i me. when it reaches wd_t i me, it triggers the watchdog action. the selected watchdog event resets the timeout counter. as trigger sources, the internal ethercat start of frame (pd i _sof), the two sp i chip select signals (pd i _sp i _csn and mfc_ctrl_sp i _csn) as well as any combination of i /o lines can be used. for the i /o lines (mfc i o00 to mfc i o23), the polarity and edge are programmable. when using an mfc i oxx pin programmed as output and as watchdog trigger, the watchdog circuitry will monitor the real output by checking the polarity of the output signal. this way, also a short circuit condition will be detected. the chip select signals respond to a rising edge (i.e. when the sp i interface loads the sp i shift register data into the corresponding registers). figure 50: structure of the mfc i o watchdog unit watchdog output port con 1 guration the following table contains the assignments of ports/signals to the con 1 guration bits in the wd_out_mask_pol register. an mfc i oxx pin programmed as output is called mfcoxx. bit # signal bit # signal 0 mfco00 polarity 32 mfco00 mask 1 mfco01 polarity 33 mfco01 mask 2 mfco02 polarity 34 mfco02 mask 3 mfco03 polarity 35 mfco03 mask 4 mfco04 polarity 36 mfco04 mask 5 mfco05 polarity 37 mfco05 mask 6 mfco06 polarity 38 mfco06 mask 7 mfco07 polarity 39 mfco07 mask 8 mfco08 polarity 40 mfco08 mask ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 183 / 204 bit # signal bit # signal 9 mfco09 polarity 41 mfco09 mask 10 mfco10 polarity 42 mfco10 mask 11 mfco11 polarity 43 mfco11 mask 12 mfco12 polarity 44 mfco12 mask 13 mfco13 polarity 45 mfco13 mask 14 mfco14 polarity 46 mfco14 mask 15 mfco15 polarity 47 mfco15 mask 16 mfco16 polarity 48 mfco16 mask 17 mfco17 polarity 49 mfco17 mask 18 mfco18 polarity 50 mfco18 mask 19 mfco19 polarity 51 mfco19 mask 20 mfco20 polarity 52 mfco20 mask 21 mfco21 polarity 53 mfco21 mask 22 mfco22 polarity 54 mfco22 mask 23 mfco23 polarity 55 mfco23 mask 24 unused/reserved 56 unused/reserved 25 unused/reserved 57 unused/reserved 26 unused/reserved 58 unused/reserved 27 unused/reserved 59 unused/reserved 28 unused/reserved 60 unused/reserved 29 unused/reserved 61 unused/reserved 30 unused/reserved 62 unused/reserved 31 unused/reserved 63 unused/reserved table 207: mfc i o watchdog wd_out_mask_pol signal/port assignment watchdog i nput port con 1 guration the following table contains the assignments of ports/signals to the con 1 guration bits in the wd_ i n_mask_pol register. an mfc i oxx pin programmed as input is called mfc i xx. bit # signal bit # signal 0 mfc i 00 polarity 32 mfc i 00 mask 1 mfc i 01 polarity 33 mfc i 01 mask 2 mfc i 02 polarity 34 mfc i 02 mask 3 mfc i 03 polarity 35 mfc i 03 mask 4 mfc i 04 polarity 36 mfc i 04 mask ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 184 / 204 bit # signal bit # signal 5 mfc i 05 polarity 37 mfc i 05 mask 6 mfc i 06 polarity 38 mfc i 06 mask 7 mfc i 07 polarity 39 mfc i 07 mask 8 mfc i 08 polarity 40 mfc i 08 mask 9 mfc i 09 polarity 41 mfc i 09 mask 10 mfc i 10 polarity 42 mfc i 10 mask 11 mfc i 11 polarity 43 mfc i 11 mask 12 mfc i 12 polarity 44 mfc i 12 mask 13 mfc i 13 polarity 45 mfc i 13 mask 14 mfc i 14 polarity 46 mfc i 14 mask 15 mfc i 15 polarity 47 mfc i 15 mask 16 mfc i 16 polarity 48 mfc i 16 mask 17 mfc i 17 polarity 49 mfc i 17 mask 18 mfc i 18 polarity 50 mfc i 18 mask 19 mfc i 19 polarity 51 mfc i 19 mask 20 mfc i 20 polarity 52 mfc i 20 mask 21 mfc i 21 polarity 53 mfc i 21 mask 22 mfc i 22 polarity 54 mfc i 22 mask 23 mfc i 23 polarity 55 mfc i 23 mask 24 unused/reserved 56 unused/reserved 25 unused/reserved 57 unused/reserved 26 unused/reserved 58 unused/reserved 27 unused/reserved 59 unused/reserved 28 unused/reserved 60 unused/reserved 29 unused/reserved 61 unused/reserved 30 unused/reserved 62 unused/reserved 31 unused/reserved 63 unused/reserved table 208: mfc i o watchdog wd_ i n_mask_pol signal/port assignment ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 185 / 204 7.20 mfc i o emergency switch i nput the mfc i o block o ? ers a dedicated emergency switch input called mfc_nes. i t is low active. i t is used to set speci 1 c mfc i oxx outputs to a a con 1 gurable safe state in case of emergency. the mfc_nes pin has weak internal pull-down resistor. a microcontroller or another circuit must actively drive a high level at mfc_nes for normal operation. the emergency switch input mfc_nes is only active if it is masked in the mfc i o_ i rq_cfg register at bit 23. otherwise it is ignored. i f mfc_nes triggers (low level), the respective outputs take their con 1 gured safe values. the internal emergency switch 2 ag remains set in register mfc i o_ i rq_flags even when the external pin mfc_nes is already driven high again. mfc_nes has impact on the following functional units and outputs: ? mfc i o pwm block : the pwm high and low side gate outputs are set to a de 1 ned con 1 gurable safe o ? -state. ? mfc i o gp i o block: all gp i os that are con 1 gured as output ports via the crossbar are set to a de 1 ned con 1 gurable safe o ? -state. ? mfc i o step and direction block : the step outputs and internal step counters freeze. ? the mfc i o_ i rq signal will be triggered. note the emergency 2 ag can only be unset be either doing a reset or by actively writing 2 times into the mfc i o_ i rq_cfg register at bit position 23. thereby, the existing i rq mask at bit 23 must 1 rst be set to zero and then set back to 1 again. this way, the internal emergency 2 ag is unset. this can be done either by the local application controller or by the ethercat master if it has access to register mfc i o_ i rq_cfg . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 186 / 204 7.21 mfc i o analog and high voltage block 7.21.1 multi voltage high current i /o lines figure 51: schematic of multi voltage i /o port output characteristics the multi voltage i /o lines allow direct driving of loads like lamps, leds or solenoids with up to 100ma output current (200ma short time peak). they can be operated in a push / pull mode, or in low current mode by using an internal pullup / pulldown resistor / current source combination. the eight multi-voltage i /os are grouped into three groups, which allow the use at the same, or di ? erent supply voltages. i n case inductive loads are driven, or loads with long interconnection cables, schottky protection diodes shall be added in order to avoid exceeding the respective supply voltage limits. a slope limited mode allows reducing electromagnetic emission by using slower switching slopes. additional 1 lter capacitors (up to 1nf recommended) may be placed on the output lines in this mode to eliminate any hf noise. the outputs provide a short to gnd and short to supply protection. when an overcurrent condition is detected, the respective mosfet remains switched o ? for the period of constant polarity. the short circuit detection features a current dependent activation time. the lower activation threshold is about 150ma. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com viox mfc_hvx mfciox.short2vs gndio outx slope controlled driver level shifter level shifter output control block slope controlled driver mfciox.weak_h mfciox.weak_l slope slope short protection 1.2v 1/2 viox input control block 17/40 viox 1s inx slope mfc_hvy mfciox.slope mfciox.differential mfciox.hv_on viox 5.5v weak low weak high 100a100a 5 mosfet 0.3v hyst. sr q differential low voltage & fast slope 10 mosfet disablels mfciox.slowslope oex outx mfciox.short2gnd disablehs 10a || 1.5m hv or slow slope tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 187 / 204 upon exceeding the activation threshold, a time proportional to the excess current is required to switch o ? the output. this way, short time peak currents can safely be switched, e.g. when long cables or capacitive loads are attached. an interrupt 2 ag informs about an active overcurrent condition. the short condition will be cleared once the output polarity is toggled. i nput characteristics the inputs automatically adapt to the supply voltage range. i n low voltage range (up to 5v operation), a fast digital schmitt trigger is used for evaluation of the input logic levels. i t provides a ttl compatible input level. i n the high voltage range, the input path switches to a threshold voltage just at half supply voltage range. both modes add a hysteresis in order to avoid oscillation with slow transitions on the inputs. when switching to slow slope operation, the input lines become 1 ltered in order to eliminate reaction to short voltage spikes. i n this mode, the half level comparator is always used. a minimum pull down current of 10 a is always drawn in order to ensure a de 1 ned level on an open input. the inputs allow a di ? erential mode between each two combined inputs (see combination table). i t is important to set both inputs to the same slope setting in this case. both input lines deliver a comparison result using each one voltage comparator. this allows direct attachment of di ? erential voltage sources like encoders. the addition of input protection resistor networks is recommended in case long cables are used. warn i ng when driving inductive loads a freewheeling diode must be provided to the high voltage i /o pins to prevent from latch-up. di ? erential input pair i nput 1 i nput 2 a mfc_hv0 mfc_hv3 b mfc_hv1 mfc_hv4 c mfc_hv2 mfc_hv5 d mfc_hv6 mfc_hv7 table 209: di ? erential input combination table the inputs are read via i nput 1 result. 7.21.2 switching regulators the tmc8462 integrates a programmable and a 1 xed buck switching regulator designed for up to 500ma of output current. the 1 xed regulator has a 1 xed output voltage of 3.3v. i ts main purpose is to supply the tmc8462 i /os and the digital part via the 1.8v linear regulators. this regulator comes with an integrated 800ma 5.5v schottky diode which minimizes part count, when an external 5v supply is available. i n case of a higher supply voltage, use an external schottky diode instead. the second regulator can be programmed to any output voltage ranging from 1.2v up to the supply voltage level. i t can be used to generate an additional 3.3v supply or any additional voltage like 5v, 12v or 24v required for operation of peripheral circuits or the high voltage i /o lines. an integrated common linear 5v regulator starts up the switch regulators. cascading of both switch regulators also is possible. both regulators support a wide range of l and c components. this is enabled by a programmable current feedback loop gain and compensation capacity. both switching regulators provide optional dampening of the coil oscillations to reduce electromagnetic emission. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 188 / 204 figure 52: i nternal schematic and external components for both switching regulators i nput voltage output voltage l sw c sw 5v 3.3v 15 h 22 f 24v 3.3v to 12v 68 h 47 f 35v 3.3v to 25v 68 h 47 f table 210: switching regulator component selection for l and c i nfo the capacitor can either be a ceramic type, or an electrolytic low-esr capacitor in parallel to a 1 f or larger ceramic capacitor. 7.21.3 analog block status register mfc i o register 59 hv_ana_status provides various status 2 ags on the actual state of the analog block. this includes: ? short to ground and short to supply detection for the hv i os ? high voltage detection 2 ags for the hv i os ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com vsx swx vreg3v3_fb saw_freq[1..0] pmos driver saw oscillator imax set sr q undervolt 1 mosfet dutycycle limit vs vdd5_out bandgap and 5v auxiliary regulator vdd5_inx switch reg supply 1.2v ref sc_disable vout_disable sc_detect c fb fb_cap[1..0] r fb fb_ampl[1..0] soft start circuit 250k sum amplifier & compa- rator + + - vout1_fb reg. 1 only 0 1.2v 1.2v ref disable uv vout_disable (reg. 1) / overtemp (3.3v reg.) sw0_diode gnd0_diode 3.3vregulatoronly 0.8a schottky 92k 53k swx_in vout1_damp reg. 1 only dampening circuit +vio c sw l sw c swe r v1 r v2 470nf sw regulator output +vs 100nf 100nf regulator 1 / 3.3v regulator tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 189 / 204 ? over-temperature detection for the hv i o circuit ? short circuit/over-current detection for the switching regulators ? over-temperature detection for the adjustable switching regulator please refer to table 184 for more details. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 190 / 204 8 electrical ratings 8.1 absolute maximum ratings note the maximum ratings may not be exceeded under any circumstances. operating the circuit at or near more than one maximum rating at a time for extended periods shall be avoided by application design. parameter symbol min max unit supply and hv i o supply voltage with t j = 0c *) v vs , v v i ox 40 v supply and hv i o supply voltage max. with t j full range *) v vs , v v i ox 35 v maximum voltage on hv i o pins v v i o -0.6 v v i ox +0.6 v peak current into hv i o input protection diodes (100ms) i hv i opeak -100 +100 ma digital i /o supply voltage v v i o 3.6 v digital vcc supply voltage (if not supplied by internal regulator) v vcc 1.98 v logic input voltage v i 3.6 v maximum current to / from digital pins and analog low voltage i /os i i o 10 ma 1.8v regulator output current (internal plus external load) i vout18 ma switching regulator repetitive short time output current i voutsw 800 ma schottky diode reverse voltage v sdr 7 v schottky diode repetitive short time forward current i sd 800 ma junction temperature t j -40 175 c storage temperature t stg -55 150 c esd-protection for interface pins (human body model, hbm) v esdap 4 (tbd.) kv esd-protection for handling (human body model, hbm) v esd 1 (tbd.) kv table 211: absolute maximum ratings for tmc8462-ba *) stray inductivity of gnd and vs connections will lead to ringing of the supply voltage when driving load. this ringing results from the fast switching slopes of the driver outputs in combination with reverse recovery of the body diodes of the output driver mosfets. even small trace inductivities as can easily generate a few volts of ringing leading to temporary voltage overshoot. this should be considered when working near the maximum voltage. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 191 / 204 8.2 operational ratings parameter symbol min max unit junction temperature t j -40 125 c high voltage supply voltage v vs,vs0,vs1 4.75 34 v digital i /o 3.3v supply voltage v vcc i o 3.15 3.45 v i /o supply voltage (high voltage mode) v v i ox 6.0 34 v i /o supply voltage (low voltage mode) v v i ox 3.0 5.5 v continuous output current single high voltage i /o i out,hv i o 100 ma continuous current into / from any high voltage i /o supply or gnd pin i i n,hv i o 200 ma switching regulator dc output current i out,sw 500 ma 3.3v switching regulator supply voltage when using internal schottky diode 4 5.5 v core supply voltage v vcc_core 1.65 1.95 v table 212: operational ratings for tmc8462-ba 8.3 dc characteristics and timing characteristics dc characteristics contain the spread of values guaranteed within the speci 1 ed supply voltage range unless otherwise speci 1 ed. typical values represent the average value of all parts measured at +25 c. temperature variation also causes stray to some values. a device with typical values will not leave min/max range within the full temperature range. 8.3.1 high voltage i /o block warn i ng when driving inductive loads a freewheeling diode must be provided to the high voltage i /o pins to prevent from latch-up. parameter symbol conditions min typ max unit hv supply current per high volt- age i /o pad i vhv i o no current driven, static mode 90 140 a r dson low side r onl t j =25 c 6 10 r dson high side r onh v v i ox =5 v; t j =25 c 10 15 r dson high side r onh v v i ox =3.3 v; t j =25 c 13 20 weak pull down current i pd 37 63 115 a weak pull up current i pu v v i ox =5 v; t j =25 c 66 110 210 a weak pull up current i pu v v i ox =3.3 v; t j =25 c 50 76 150 a ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 192 / 204 parameter symbol conditions min typ max unit over-current protection activa- tion threshold sourcing i och output sourcing cur- rent -100 -150 -500 ma over-current protection activa- tion threshold sinking i ocl output sinking cur- rent 100 150 500 ma 200ma sink current capability time limit t ocl200 output sinking cur- rent 10 s switching slope (slow) rising t hvolh 10% to 90% 100 200 500 ns switching slope (slow) falling t hvohl 90% to 10% 100 200 500 ns switching slope (fast) rising t hvolh 10% to 90% 20 ns switching slope (fast) falling t hvohl 90% to 10% 20 ns i nput 1 lter time constant t hv i f slow slope setting 750 1000 1500 ns i nput threshold (lv mode) v hv i lll i nput going low, v v i ox =5.5 v 0.8 v i nput threshold (lv mode) v hv i hll i nput going high, v v i ox =5.5 v 1.6 v i nput hysteresis (lv mode) v hv i hystl v v i ox =5.5 v 0.1 0.3 v i nput threshold (hv mode) v hv i hlh i nput going high 0.5 v v i o v i nput threshold (hv mode) v hv i llh i nput going low 0.43 v v i o v i nput hysteresis (hv mode) v hv i hysth 0.075 v v i o v di ? erential mode input o ? set voltage (lv mode and fast slope) v hv i d common mode volt- age >=0.5 v -10 0 +10 mv di ? erential mode input o ? set voltage (hv mode or slow slope setting) v hv i d common mode volt- age >=2 v -150 0 +150 mv i nput delay (300mv step) di ? erential mode, fast slope 100 ns i nput current per high voltage i /o pad (hv mode) i hv i oh v hv i o = v v i ox = 24 v 26 50 a i nput current per high voltage i /o pad (lv mode) i hv i oh v hv i o = v v i ox = 3.0 v to 5 v 10 15 a table 213: high voltage i /o block dc characteristics 8.3.2 switching regulators parameter symbol conditions min typ max unit hv supply current per high voltage i /o pad i vhv i o no current driven, static mode 90 140 a ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 193 / 204 parameter symbol conditions min typ max unit r dson power switch r on t j =25 c 1 1.5 over-current protection activation threshold sourcing i och output sourc- ing current 800 1200 1600 ma oscillator frequency f osc setting 00 (de- fault) 240 khz setting 01 130 setting 10 470 setting 11 890 duty cycle limit dl 83 % schottky diode forward voltage v sdf i =350ma 0.60 0.80 v soft startup time 1 ms 5v auxiliary voltage regulator output voltage v vdd5_out 4.75 5 5.25 v 5v auxiliary voltage regulator output current limit i vdd5_out 10 mv table 214: switching regulator dc characteristics 8.3.3 digital i os all i /o lines include schmitt-trigger inputs to enhance noise margin. parameter symbol conditions min typ max unit i nput voltage low level v i nl v vcc i o = 3.3v -0.3 0.8 v i nput voltage high level v i nh v vcc i o = 3.3v 2.3 3.6 v i nput with pull-down v i n = 3.3v 5 30 110 a i nput with pull-up v i n = 0v -110 -30 -5 a i nput low current v i n = 0v -10 10 a i nput high current v i n = v dd -10 10 a output voltage low level v outl v vcc i o = 3.3v 0.4 v output voltage high level v outh v vcc i o = 3.3v 2.64 v output driver strength standard i out_drv 4 ma output driver strength led outputs i out_led 8 ma driver strength nreset i /o pin i out_rst driven by internal un- dervoltage detectors high/low 5 30 a table 215: digital i os dc characteristics ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 194 / 204 9 manufacturing data 9.1 package dimensions figure 53: tmc8462-ba package outline drawing ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 195 / 204 symbol min normal max total thickness a 1.4 stand o ? a1 0.27 0.37 substrate thickness a2 0.26 ref mold thickness a3 0.7 ref body size d 9 bsc body size e 9 bsc ball diameter 0.4 ball opening 0.3 ball width b 0.37 0.47 ball pitch e 0.75 bsc ball count n 121 edge ball center to center d1 7.5 bsc edge ball center to center e1 7.5 bsc body center to contact ball sd bsc body center to contact ball se bsc package edge tolerance aaa 0.1 mold 2 atness bbb 0.2 coplanarity ddd 0.12 ball o ? set (package) eee 0.15 ball o ? set (ball) ? f 0.08 table 216: dimensions of tmc8462-ba ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 196 / 204 9.2 marking the device marking is shown below. pin 1 location is highlighted with a dot. yyww = date code. lllll = lot number. figure 54: tmc8462-ba device marking 9.3 board and layout considerations ? example part libraries for di ? erent cad tools are available as downloads on the respective i c product page on the tr i nam i c website at https://www.trinamic.com/products/integrated-circuits/ . ? package drawings, recommended land patterns, and soldering pro 1 les for all tr i nam i c i c packages are available online at https://www.trinamic.com/support/help-center/ic-packages/ ? tr i nam i c s evaluation boards are fully available as layout examples and recommendations and are free for download. design data, gerber data, and additional information is available at https: //www.trinamic.com/support/eval-kits/ . ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 197 / 204 10 abbreviations abbreviation description mcu microcontroller unit, application controller al application layer as i c application speci 1 c i ntegrated circuit coe can application protocol over ethercat comm common anode or common cathode cpu central processing unit dc distributed clocks dpram dual ported random access memory ecat ethercat en i ethercat network i nformation ( i nformation on network con 1 guration in xml format) eof end of frame esc ethercat slave controller es i ethercat slave i nformation (device description/con 1 guration data in xml format) esm ethercat state machine etg ethercat technology group ethercat ethernet for control automation technology fmmu fieldbus memory management unit foe file access over ethercat gp i o general purpose i /o gp i general purpose i nput gpo general purpose output i de i ntegrated development environment i ec i nternational electrotechnical commission i rq i nterrupt request led light emitting diode m i (phy) management i nterface m ii media i ndependent i nterface m i so master i n - slave out mos i master out - slave i n pd i process data i nterface pdo process data object pdram process data random access memory ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 198 / 204 pof passive optical fiber rms root mean square value s ii slave i nformation i nterface sm syncmanager sof start of frame sp i serial peripheral i nterface tmcl tr i nam i c motion control language (s)tpc (shielded) twisted pair copper ttl transistor transistor logic uart universal asynchronous receiver transmitter usb universal serial bus xml extended mark-up language table 217: abbreviations used in this manual ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 199 / 204 11 tmc8462-ba errata 11.1 case 1 C lost link counters description the tmc8462 features lost link error counters for each of the two m ii ports. the lost link counters can be read from esc addresses 0x0310 and 0x0311. see also section 6.4.8.6 . the observed behavior is that after reset and after power cycling each counter already shows a value of 1 (one) but it should be 0 (zero). regardless if there is a physical tpc cable connection to a master or another slave or not. this behavior is repeatable. the same e ? ect (increasing the counter) can be achieved by manually disconnecting and re-connecting a tpc cable from an active port. i mpact on applications there is no known impact on the application. the lost link counters are for diagnosis only and do not have a direct impact on other functions of the ethercat slave controller. root cause the l i nk/act leds also show a very short pulse of ca. 250 milliseconds after reset and power-cycling which internally lead to a single increment of the lost link counters. the root cause for this behavior is not yet identi 1 ed. possible workaround there is no workaround available yet. please check for updates. ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 200 / 204 12 figures i ndex 1 general device architecture . . . . . . 7 2 tmc8462 evaluation board . . . . . . 11 3 tmc8462 breakout board for rj45 and tpc . . . . . . . . . . . . . . . . . . . . 12 4 tmcl- i de . . . . . . . . . . . . . . . . . 12 5 con 1 guration wizard example C mfc i o block con 1 guration . . . . . . 13 6 con 1 guration wizard example C s ii eeprom content and c-code output 14 7 tmc8462-ba pinout top view . . . . . 15 8 pd i control signals . . . . . . . . . . . 23 9 pd i sp i 2 byte addressing . . . . . . . 24 10 pd i sp i 3 byte addressing . . . . . . . 25 11 sp i timing example . . . . . . . . . . . 26 12 mfc control signals . . . . . . . . . . . 27 13 mfc ctrl sp i 2 byte addressing . . . 28 14 mfc ctrl sp i 3 byte addressing . . . 28 15 mfc sp i timing example . . . . . . . . 28 16 sp i bus sharing . . . . . . . . . . . . . 29 17 physical bus interface pins . . . . . . . 30 18 minimum external circuit for power- on reset . . . . . . . . . . . . . . . . . . 31 19 pll supply 1 lter . . . . . . . . . . . . . 31 20 phy power regulator 1 ltering . . . . . 32 21 external circuit for switching regulator 0 with vs0 = 5v . . . . . . . . . . . . . 33 22 external circuit for switching regulator 0 with vs0 > 5v . . . . . . . . . . . . . 33 23 external circuit for adjustable buck regulator . . . . . . . . . . . . . . . . . 34 24 minimum external supply circuit for single 3.3v supply . . . . . . . . . . . . 35 25 minimum external supply circuit for single 5v supply . . . . . . . . . . . . . 36 26 minimum external supply circuit for single supply >5v . . . . . . . . . . . . 37 27 typical power supply chain using both buck converters . . . . . . . . . . . . . 38 28 status led circuit . . . . . . . . . . . . 38 29 s ii eeprom circuit (shown for eep- roms >32kbit) . . . . . . . . . . . . . . 39 30 direct phy to phy connection . . . . . 39 31 mfc i o block con 1 guration using the esc parameter ram . . . . . . . . . . 111 32 mfc i o crossbar example con 1 guration 151 33 mfc i o es i /xml con 1 guration block . 157 34 mfc i o i ncremental encoder unit . . 158 35 block structure of sp i master unit . . 160 36 block structure of sp i master unit . . 165 37 block structure of the mfc i o step and direction block . . . . . . . . . . . . . 169 38 step & direction signal timing . . . . 170 39 block structure of the mfc i o pwm block . . . . . . . . . . . . . . . . . . . 172 40 pwm chopper modes . . . . . . . . . 174 41 pwm timing (centered pwm) . . . . . 175 42 pwm timing (left aligned pwm) . . . . 175 43 pwm timing (right aligned pwm) . . . 176 44 pwm bbm timing . . . . . . . . . . . . 176 45 centered pwm with pwm channel 2 shifted from center (example showing only 3 pwm channels) . . . . . . . . . 177 46 rc 1 lter for dac output with example values . . . . . . . . . . . . . . . . . . . 178 47 block structure of gp i o unit . . . . . 179 48 block structure of the mfc i o i rq block180 49 logical position of the mfc i o watch- dog unit between crossbar and mf- c i oxx pins . . . . . . . . . . . . . . . . 181 50 structure of the mfc i o watchdog unit 182 51 schematic of multi voltage i /o port . 186 52 i nternal schematic and external com- ponents for both switching regulators 188 53 tmc8462-ba package outline drawing 194 54 tmc8462-ba device marking . . . . . 196 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 201 / 204 13 tables i ndex 1 tmc8462 order codes . . . . . . . . . 6 2 pin and signal description for tmc8462-ba . . . . . . . . . . . . . . . 22 3 pd i signal description . . . . . . . . . 24 4 pd i sp i commands . . . . . . . . . . . 24 5 mfc ctrl sp i signal description . . . 27 6 physical bus interface pin description 30 7 available ethercat chip features (0 = not available/disabled, 1 = avail- able/enabled . . . . . . . . . . . . . . . 42 8 tmc8462 ethercat registers . . . . . 48 9 register 0x0000 (type) . . . . . . . . . 49 10 register 0x0001 (revision) . . . . . . . 49 11 register 0x0002 (build) . . . . . . . . . 49 12 register 0x0004 (fmmus) . . . . . . . 50 13 register 0x0005 (sms) . . . . . . . . . 50 14 register 0x0006 (ram size) . . . . . . 50 15 register 0x0007 (port descriptor) . . 51 16 register 0x0008:0x0009 (esc features) 52 17 register 0x0010:0x0011 (station addr) 53 18 register 0x0012:0x0013 (station alias) 53 19 register 0x0020 (write register enable) 54 20 register 0x0021 (write register prot.) 54 21 register 0x0030 (esc write enable) . 54 22 register 0x0031 (esc write prot.) . . . 55 23 register 0x0040 (esc reset ecat) . . 56 24 register 0x0041 (esc reset pd i ) . . . 56 25 register 0x0100:0x0103 (dl control) . 58 26 register 0x0108:0x0109 (r/w o ? set) 58 27 register 0x0110:0x0111 (dl status) . 60 28 decoding port state in esc dl status register 0x0111 (typical modes only) . 60 29 register 0x0120:0x0121 (al cntrl) . . 61 30 register 0x0130:0x0131 (al status) . 62 31 register 0x0134:0x0135 (al status code) 62 32 register 0x0138 (run led override) . 63 33 register 0x0139 (err led override) . 63 34 register 0x0140 (pd i control) . . . . . 64 35 register 0x0141 (esc con 1 g) . . . . . 64 36 register 0x014e (pd i i nformation)) . . 65 37 register 0x0150 (pd i sp i cfg) . . . . . 66 38 register 0x0151 (sync/latch cfg) . 67 39 register 0x0152:0x0153 (pd i sp i extcfg) 67 40 register 0x0200:0x0201 (ecat event m.) 68 41 register 0x0204:0x0207 (al event mask) 68 42 register 0x0210:0x0211 (ecat event r.) 69 43 register 0x0220:0x0223 (al event r.) 70 44 register 0x0300:0x0307 (rx err cnt) . 71 45 register 0x0308:0x030b (fw rx err cnt) 71 46 register 0x030c (proc. unit err cnt) . 71 47 register 0x030d (pd i err cnt) . . . . . 72 48 register 0x030e (pd i err code) . . . . 72 49 register 0x0310:0x0313 (ll counter) 73 50 register 0x0400:0x0401 (wd divider) 74 51 register 0x0410:0x0411 (wd time pd i ) 74 52 register 0x0420:0x0421 (wd time pd) 74 53 register 0x0440:0x0441 (wd status pd) 75 54 register 0x0442 (wd counter pd) . . 75 55 register 0x0443 (wd counter pd i ) . . 76 56 s ii eeprom i nterface register overview 77 57 register 0x0500 (prom con 1 g) . . . . 77 58 register 0x0501 (prom pd i access) . 77 59 register 0x0502:0x0503 (prom cntrl) 79 60 register 0x0504:0x0507 (prom address) 79 61 register 0x0508:0x050f (prom data) 80 62 register 0x0580:0x05e1 (mfc i o con 1 g) 81 63 m ii management i nterface register overview . . . . . . . . . . . . . . . . . 82 64 register 0x0510:0x0511 (m i cntrl/state) 83 65 register 0x0512 (phy address) . . . . 83 66 register 0x0513 (phy register address) 84 67 register 0x0514:0x0515 (phy data) . 84 68 register 0x0516 (m i ecat state) . . . 84 69 register 0x0517 (m i pd i state) . . . . 85 70 register 0x0518+y (phy port status) . 85 71 fmmu register overview . . . . . . . 86 72 register 0x06y0:0x06y3 (log start addr) 86 73 register 0x06y4:0x06y5 (fmmu length) 86 74 register 0x06y6 (log. start bit) . . . . 87 75 register 0x06y7 (log. stop bit)) . . . . 87 76 register 0x06y8:0x06y9 (phy. start addr 87 77 register 0x06ya (phy. start bit) . . . . 87 78 register 0x06yb (fmmu type) . . . . . 88 79 register 0x06yc (fmmu activate) . . . 88 80 register 0x06yd:0x06yf (reserved) . 88 81 syncmanager register overview . . . 89 82 register 0x0800+y*8:0x0801+y*8 (phy. start addr) . . . . . . . . . . . . . . . . 89 83 register 0x0802+y*8:0x0803+y*8 (sm length) . . . . . . . . . . . . . . . . . . 89 84 register 0x0804+y*8 (sm control) . . 90 85 register 0x0805+y*8 (sm status) . . . 91 86 register 0x0806+y*8 (sm activate) . . 91 87 register 0x0807+y*8 (sm pd i control) 92 88 register 0x0900:0x0903 (rcv time p0) 93 89 register 0x0904:0x0907 (rcv time p1) 93 90 register 0x0910:0x0917 (system time) 94 91 register 0x0918:0x091f (rcv time epu) 94 92 register 0x0920:0x0927 (sys time o ? - set) . . . . . . . . . . . . . . . . . . . . 95 93 register 0x0928:0x092b (sys time de- lay) . . . . . . . . . . . . . . . . . . . . 95 94 register 0x092c:0x092f (sys time di ? ) 95 95 register 0x0930:0x931 (speed cnt start) 96 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 202 / 204 96 register 0x0932:0x0933 (speed cnt di ? ) 96 97 register 0x0934 (sys time di ? filter) . 97 98 register 0x0935 (speed cnt filter depth) 97 99 register 0x0980 (cyclic unit cntrl) . . 98 100 register 0x0981 (sync out activation) 99 101 register 0x0982:0x0983 (sync pulse length) . . . . . . . . . . . . . . . . . . 100 102 register 0x0984 (activation status) . . 100 103 register 0x098e (sync0 status) . . . . 100 104 register 0x098f (sync1 status) . . . . 101 105 register 0x0990:0x0997 (start time cyclic operation) . . . . . . . . . . . . 101 106 register 0x0998:0x099f (next sync1) 101 107 register 0x09a0:0x09a3 (sync0 cycle time) . . . . . . . . . . . . . . . . . . . 102 108 register 0x09a4:0x09a7 (sync1 cycle time) . . . . . . . . . . . . . . . . . . . 102 109 register 0x09a8 (latch0 control) . . . 103 110 register 0x09a9 (latch1 control) . . . 103 111 register 0x09ae (latch0 status) . . . . 104 112 register 0x09af (latch1 status) . . . . 104 113 register 0x09b0:0x09b7 (latch0 time pos edge) . . . . . . . . . . . . . . . . . 105 114 register 0x09b8:0x09bf (latch0 time neg edge) . . . . . . . . . . . . . . . . 105 115 register 0x09c0:0x09c7 (latch1 time pos edge) . . . . . . . . . . . . . . . . . 106 116 register 0x09c8:0x09cf (latch1 time neg edge) . . . . . . . . . . . . . . . . 106 117 register 0x09f0:0x09f3 (ecat bu ? er change event time) . . . . . . . . . . . 107 118 register 0x09f8:0x09fb (pd i bu ? er start event time) . . . . . . . . . . . . 107 119 register 0x09fc:0x09ff (pd i bu ? er change event time) . . . . . . . . . . . 107 120 register 0x0e00:0x0e07 (product i d) . 108 121 register 0x0e08:0x0e0f (vendor i d) . 108 122 process data ram (0x1000:0xffff) . . 109 123 process data ram size . . . . . . . . . 109 124 mfc i o register overview for tmc8462-ba . . . . . . . . . . . . . . . 114 125 mfc i o register 0 C enc_mode . . . 115 126 mfc i o register 1 C enc_status . . . 116 127 mfc i o register 2 C x_enc (write) . . 116 128 mfc i o register 3 C x_enc (read) . . . 116 129 mfc i o register 4 C enc_const . . . 116 130 mfc i o register 5 C enc_latch . . . 117 131 mfc i o register 6 C sp i _rx_data . . . 118 132 mfc i o register 7 C sp i _tx_data . . . 118 133 mfc i o register 8 C sp i _conf . . . . . 119 134 mfc i o register 9 C sp i _status . . . . 119 135 mfc i o register 10 C sp i _length . . 119 136 mfc i o register 11 C sp i _t i me . . . . 119 137 mfc i o register 12 C i 2c_t i mebase . 120 138 mfc i o register 13 C i 2c_control . 120 139 mfc i o register 14 C i 2c_status . . . 120 140 mfc i o register 15 C i 2c_address . . 121 141 mfc i o register 16 C i 2c_data_r . . . 121 142 mfc i o register 17 C i 2c_data_w . . 121 143 mfc i o register 18 C sd_ch0_steprate 122 144 mfc i o register 19 C sd_ch1_steprate 122 145 mfc i o register 20 C sd_ch2_steprate 122 146 mfc i o register 21 C sd_ch0_stepcount 123 147 mfc i o register 22 C sd_ch1_stepcount 123 148 mfc i o register 23 C sd_ch2_stepcount 123 149 mfc i o register 24 C sd_ch0_steptarget 123 150 mfc i o register 25 C sd_ch1_steptarget 124 151 mfc i o register 26 C sd_ch2_steptarget 124 152 mfc i o register 27 C sd_ch0_compare 124 153 mfc i o register 28 C sd_ch1_compare 125 154 mfc i o register 29 C sd_ch2_compare 125 155 mfc i o register 30 C sd_ch0_nextsr 125 156 mfc i o register 31 C sd_ch1_nextsr 125 157 mfc i o register 32 C sd_ch2_nextsr 126 158 mfc i o register 33 C sd_steplength 126 159 mfc i o register 34 C sd_delay . . . . 126 160 mfc i o register 35 C sd_cfg . . . . . 127 161 mfc i o register 36 C pwm_cfg . . . . 128 162 mfc i o register 37 C pwm1 . . . . . . 129 163 mfc i o register 38 C pwm2 . . . . . . 129 164 mfc i o register 39 C pwm3 . . . . . . 129 165 mfc i o register 40 C pwm4 . . . . . . 129 166 mfc i o register 41 C pwm1_cntrshft 130 167 mfc i o register 42 C pwm2_cntrshft 130 168 mfc i o register 43 C pwm3_cntrshft 130 169 mfc i o register 44 C pwm4_cntrshft 130 170 mfc i o register 45 C pwm_pulse_b_pulse_a 131 171 mfc i o register 46 C pwm_pulse_length 131 172 mfc i o register 47 C gpo . . . . . . . 132 173 mfc i o register 48 C gp i . . . . . . . . 132 174 mfc i o register 49 C gp i o_conf i g . 132 175 mfc i o register 50 C dac_val . . . . 133 176 mfc i o register 51 C mfc i o_ i rq_cfg 134 177 mfc i o register 52 C mfc i o_ i rq_flags 135 178 mfc i o register 53 C wd_t i me . . . . 136 179 mfc i o register 54 C wd_cfg . . . . . 136 180 mfc i o register 55 C wd_out_mask_pol 137 181 mfc i o register 56 C wd_oe_pol . . 137 182 mfc i o register 57 C wd_ i n_mask_pol 138 183 mfc i o register 58 C wd_max . . . . 138 184 mfc i o register 59 C hv_ana_status 139 185 mfc i o register 63 C sync1_sync0_event_cnt 139 186 mfc i o register 64 C hv i o_cfg . . . . 140 187 mfc i o register 65 C buck_conv_cfg 142 188 mfc i o register 66 C al_overr i de . 143 189 eeprom parameter map . . . . . . . . 147 190 crossbar con 1 guration values . . . . 150 191 slope slow/weak high/weaklow con 1 g 152 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 203 / 204 192 di ? erential hv input con 1 guration . . 152 193 con 1 guration bits for 3.3v switching regulator . . . . . . . . . . . . . . . . . 153 194 con 1 guration bits for adjustable switching regulator . . . . . . . . . . . 154 195 register mapping example . . . . . . 155 196 register con 1 guration byte . . . . . . 156 197 trigger source descriptions . . . . . . 156 198 sp i mode con 1 guration . . . . . . . . 161 199 i 2c control commands . . . . . . . . . 165 200 i 2c status register bits . . . . . . . . . 166 201 i 2c status overview . . . . . . . . . . . 166 202 i 2c addres register . . . . . . . . . . . 167 203 step and direction unit parameters . 170 204 pwm unit parameters . . . . . . . . . 173 205 pwm modes . . . . . . . . . . . . . . . 173 206 gpo signal output states . . . . . . . . 179 207 mfc i o watchdog wd_out_mask_pol signal/port assignment . . . . . . . . . 183 208 mfc i o watchdog wd_ i n_mask_pol signal/port assignment . . . . . . . . . 184 209 di ? erential input combination table . 187 210 switching regulator component selec- tion for l and c . . . . . . . . . . . . . 188 211 absolute maximum ratings for tmc8462-ba . . . . . . . . . . . . . . . 190 212 operational ratings for tmc8462-ba 191 213 high voltage i /o block dc characteris- tics . . . . . . . . . . . . . . . . . . . . . 192 214 switching regulator dc characteristics 193 215 digital i os dc characteristics . . . . . 193 216 dimensions of tmc8462-ba . . . . . . 195 217 abbreviations used in this manual . . 198 218 i c revision . . . . . . . . . . . . . . . . 204 219 document revision . . . . . . . . . . . 204 ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com tmc8462 datasheet ? document revision v1.4 ? 2018-may -09 204 / 204 14 revision history 14.1 i c revision version date author description v1.0 01.07.2016 sk, sl, bd, hs silicon v1.0 v1.1 01.09.2017 sk, sl, bd, hs silicon v1.1 v1.11 01.11.2017 sk, sl, bd, hs silicon v1.11 table 218: i c revision 14.2 document revision version date author description v1.00 01.09.2017 sk, sl, bd i nitial release version v1.10 01.12.2017 sk, sl, bd updated for 1 nal product version v1.20 19.03.2018 sk, bd added latch-up warning for high voltage i os v1.30 13.04.2018 sk, ok i ntra-document references 1 xed v1.40 09.05.2018 sk added errata table 219: document revision ?2018 tr i nam i c motion control gmbh & co. kg, hamburg, germany terms of delivery and rights to technical change reserved. download newest version at www.trinamic.com |
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